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When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select whether to implement the function using hardware DSP blocks or only device logic, pipeline latency e.t.c. Is there a way to specify such things in VHDL at all?

Dividers are the slowest of the 4 operations (+, -, *, /). Using the / operator in VHDL means that we want a divider that can complete its task in a single cycle. This would generate a lot of logic and reduce Fmax of the design. How do I tell the synthesis tool to infer a divider that has pipeline latency of e.g 5 cycles in this case, without instantiating the actual divider from the IP catalogue.

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  • \$\begingroup\$ Your question can not be answered as it depends greatly on the vendor. The most likely answer will be: "Read The Vendor IP Manuals." Also your statement " the synthesis tool shall infer the appropriate IP block" is rather bold. Not all vendors support a divider IP. \$\endgroup\$ – Oldfart Dec 4 '18 at 21:19
  • \$\begingroup\$ I am being specific to Quartus. Lets focus on Quartus only for this one. \$\endgroup\$ – quantum231 Dec 4 '18 at 21:20
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Sticking with Intel FPGA tools. I have recently had this exact same question.

The short answer is that you can't do what you want to do. Quartus does not allow you to specify pipe latency just using a divide operator. It's unlikely that any tool would as the divide operator is defined by the language and is overloaded by the single most common package in the language: Numeric_std.

The long answer is; you could do this if you wrote your own overloaded version of the divide operator which is, in VHDL, just a function after all. You could somehow link this to an instantiation of a divider module (create a divider elsewhere to obtain the HDL code created by the wizard. This matches the pattern the tools use to recognise a divider. Or write your own for fun) and insert the number of stages into the Generic Map.

You could then analyse the RTL and Technology Map viewers to ensure that what you've specified has actually inferred either DSP modules (if the device supports this) or the most efficient logic for a divide operation in this device.

You could then test out if you meet all the myriad timing requirements.

After all that, you can do what you want to do. Maybe.

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