When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select whether to implement the function using hardware DSP blocks or only device logic, pipeline latency e.t.c. Is there a way to specify such things in VHDL at all?
Dividers are the slowest of the 4 operations (+, -, *, /). Using the / operator in VHDL means that we want a divider that can complete its task in a single cycle. This would generate a lot of logic and reduce Fmax of the design. How do I tell the synthesis tool to infer a divider that has pipeline latency of e.g 5 cycles in this case, without instantiating the actual divider from the IP catalogue.