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I am trying to understand hardware Caches. I have some understanding, and I would like to ask if my understanding is correct.

I understand that there are three types of cache mapping; direct, full associative and set associative.

I would like to know, is the type of mapping implemented with logic gates in hardware and specific to say some computer system and in order to change the mapping, one would be required to changed the electrical connections?

My current understanding is that in RAM, there exists a memory address to refer to each block of memory. Within a block contains words, each words contain a number of bytes. We can represent the number of options with number of bits. So for example, 4096 memory locations, each memory location contains 16 bytes. If we were to refer to each byte then 2^12*2^4 = 2^16 16 bit memory address would be required to refer to each byte.

The cache also has a memory address, valid bit, tag, and some data capable of storing a block of main memory of n words and thus m bytes. Where m = n*i (bytes per word)

For an example, direct mapping 1 block of main memory can only be at one particular memory location in cache. When the CPU requests for some data using a 16bit memory location of RAM, it checks for cache first. How does it know that this particular 16bit memory address can only be in a few places?

My thoughts are, there could be some electrical connection between every RAM address to a cache address. The 16bit address could then be split into parts, for example only compare the left 8bits with every cache memory address, then if match compare the byte bits, then tag bits then valid bit

Is my understanding correct? Thank you! Really do appreciate if someone read this long post

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The connection with ram address and cache address is the lower bits of the address. So RAM address 0x101111 (6 bit address as example) can always be found at cache address 0x111 with tag 0x101.

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