- What is the reason for D1, C1, R3 elements at input? Why I can’t just tie a transistor base to the trigger input, without these elements?
- I've read that Vcc voltage can’t be as high as you would and it has some max value, but I can’t determine what it is and where it comes from.
The steady-state of this circuit, removing C2 to find that steady-state, is with T1 (the right bipolar) on, and that collector voltage low, thus taking away any bias current into T2.
Steady-state is with rightmost transistor on/saturated and left most transistor off(cutoff).
Now bring in a rising edge to C1. (negative edges are blocked by the diode). If your input amplitude is at least 2 diode drops, and the pulse source resistance << Rs (the feedback resistor), then left transistor turns on and drives its collector near to ground.
You are injecting a trigger pulse, thru the high-pass-filter of C1 and R3. There is a propagation delay around the feedback loop; the rightmost transistor needs time to flush out charges from the collector junction, so that transistor can exit the saturation-mode and that collector can rise enough to provide current through Rs to base of left transistor, and replace the pulse-current flowing through C1/D1.
Your input pulse width must exceed T_on of the left transistor, and T_delay+T_off of the right transistor; plan on at least 50nS to 200nS.
Notice the high quiescent (steady-state) voltage across C2: Vdd - 0.6 volts, or about 4.4 volts.
If the VDD > emitter-base breakdown voltage, the negative swing on base of right transistor is clamped at the Zener (VbeReverse) voltage, and your computed time-constant is no longer valid.