Given a particular circuit of TTL, can I calculate how much time it will take for an electrical signal to propagate through some section, or all of, the circuit?

If I wanted to know how long it takes an electrical signal to move from a point A to a point B in a given TTL circuit, how would I calculate that?

If I have a circuit with a system clock (very basic TTL computer architecture), can I calculate how long it will take an electrical signal to move through the entire system after a single CPU clock pulse?

I'd really like a way to calculate this theoretically rather than only testing a circuit to somehow derive this information, but I would also appreciate knowing how I could test a circuit to find this information.

  • \$\begingroup\$ Wiki - speed of electricity and Wiki - electron drift velocity. \$\endgroup\$ – Andy aka Dec 7 '18 at 9:29
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    \$\begingroup\$ I think what you are looking for is not how fast the electrons move, but the delay with which information is transferred. This will depend on the speed of EM radiation (voltage/current is an EM wave) in the medium/wire \$\endgroup\$ – ijuneja Dec 7 '18 at 9:44
  • \$\begingroup\$ Since you mentioned TTL, the delay it takes for EM radiation to propagate is negligible compared to the time it takes to change the state of transistors. What you might be looking for is 'Digital Delay' \$\endgroup\$ – ijuneja Dec 7 '18 at 9:46
  • \$\begingroup\$ Are you sure you want the time for the electricity, the electrons? Normally in a design with a clock you should be looking for 'propagation delay'. The time it takes a signal to travel through a number of gates. As to the clock signal itself: look for "clock distribution" and "clock tree". \$\endgroup\$ – Oldfart Dec 7 '18 at 10:30
  • \$\begingroup\$ Pardon me for any incorrect terminology. For what I'm actually trying to accomplish, I'd like to be able to calculate how much time it takes for (electricity? signal?) to move through a particular part/section of a circuit within a computer architecture, whether that section is a single gate, a group of gates, or some larger system. I'd like to be able to modify the design of a computer's architecture and understand its fastest possible clock speed given the changes to its design. \$\endgroup\$ – Christian Westbrook Dec 7 '18 at 11:04

For a TTL circuit of discrete gates and flip flops (we are not talking about internal delays within complex logic here), it is possible, but it won't be particularly accurate.

You can get the minimum and maximum total time provided the data sheet gives you min and max for \$t_{PLH}\$ and \$t_{PHL}\$ (propagation delay low to high and high to low respectively).

From the datasheet for the venerable 74ALS04, I can see that the propagation delay is between 3 to 11 nsec for \$t_{PLH}\$ and between 2 to 8 nsec for \$t_{PHL}\$ 74ALS04 propagation delay

The test measurement from the datasheet shows just how the measurement is defined: 74LS04 Propagation delay definition

Note that the transition type is referred to the output change of state.

You can simply look up each gate and extract the information from the datasheet, but as the propagation delay differs from low to high and high to low (not true of all parts) it could get a bit tedious, but can it be done for a TTL circuit of individual gates and flip flops? Sure.

For clocked circuitry, look up the 74LAS74 or perhaps the 74ALS374.


I'd like to be able to calculate how much time it takes for (electricity? signal?) to move through a particular part/section of a circuit within a computer architecture...

That is what the "static timing analyser" of a synthesis tools does. The synthesis tools will adapt the used gates to meet the giving timing requirements. In that it will select the optimum gates, chose from various adders, do register multiplication, register balancing and use various other strategies to make the circuit meet timing. In that it will also estimate the 'wire load' depending on the area of the circuit.

This task has moved away from 'humans' as it is way, way, too complex to do manually.

The worth of a digital VLSI designer nowadays lies in the experience she/he has gained over the years to have a 'feel' for how the logic/RTL should look like to meet the required clock frequency.

  • \$\begingroup\$ +1 This is really the best answer and the only way to get useful data. Changes at the architecture level can have unintended consequences when they are actually implemented as gates and wires. Trying to evaluate architectural changes without synthesizing to gates is a fool's errand. \$\endgroup\$ – Elliot Alderson Dec 7 '18 at 13:24

Basically, this is very hard to do from first principles. As a realistic project, I'd have to rate it up near impossible.

First, you need to know the internal circuit which the gate uses. Note that this is not the "equivalent" circuit which you can find on some data sheets - you need the complete circuit.

Next, you need good models of the parts used in the circuit, most especially the transistors. And these are not available - the transistors were not developed for independent release, so the detailed parameters were not published.

Then you need the "implied" parts of the circuit - channel resistances and capacitances, plus the modelling of the IC package and bonding wires. Note that the latter became important with the development of very high-speed gates in the 80's and the issue of ground bounce. Internal capacitances, in particular, play a big part in determining gate speed, and these depend very much on the details of part layout in the IC.

If you have all of that, determining the gate speed is pretty straightforward.

Lots of luck.


Electrons in copper wire drift at upto a few milimeteres per second, faster causes excessive heating in the wires.

Electrons "orbit" atoms faster than a speeding bullet.

Electric signals typically propagate at more than half the speed of light.


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