I don't know what is the problem in my design. I've been changing the values of the linking capacitors but didn't get any result.
closed as unclear what you're asking by Dwayne Reid, RoyC, Finbarr, MCG, clabacchio♦ Dec 11 '18 at 12:45
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The 1st stage collector output is a current sink driving a small pullup R shunted by CC load such that the cap attenuates the voltage gain above 1/RC. So you have a mismatch. Move the CC cap. to the emitter.
The 2nd stage emitter output is shorted the CE cap such that it attenuates the signal to a flat line. Remove CE.
1st look at R ratios for DC bias , then impedance ratios for AC gain then loading ratios between stages. Then look at large signal clipping and Power dissipation and make adjustments.