Is the effective resistance mentioned in the image the input resistance for the CPLD pins? I am using Vccio at 3.3 V.
(Image is from Xilinx CPLD IO guide application note).
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No, it is the impedance of the circuitry that implements a pull-up or keeper. The input impedance will typically be much larger, and is usually specified as a maximum input current over some range of voltages.