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enter image description here

Is the effective resistance mentioned in the image the input resistance for the CPLD pins? I am using Vccio at 3.3 V.

(Image is from Xilinx CPLD IO guide application note).

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No, it is the impedance of the circuitry that implements a pull-up or keeper. The input impedance will typically be much larger, and is usually specified as a maximum input current over some range of voltages.

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  • \$\begingroup\$ thank you for answering , i can't find any mentioning on input current at the datasheet .Can i ask you something more ? \$\endgroup\$ – Suparman Sy Dec 11 '18 at 10:04
  • \$\begingroup\$ Look for a table of "DC Electrical Characteristics" in the device datasheet. Xilinx calls this parameter "Input Leakage Current". \$\endgroup\$ – Elliot Alderson Dec 11 '18 at 16:22

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