The first graph is what a forward bias SOA (Safe Operating Area) graph looks like in general. Below is a real graph from the TIP31 datasheet:
The limits are defined by maximum Vceo, maximum Ic, thermal limit, bonding wire limit and secondary breakdown.
The second is reverse bias SOA (base is reverse biased). Here is an actual graph from an MJ10021 datasheet:
You can see that the allowable instantaneous power at turn-off is dramatically lower for high Vce. More info here. In particular, pay attention to temperature derating effects.
In both cases, you must remain below and to the the left of the contour lines under all conditions or the transistor may be damaged.
The thermal timeconstant for silicon of size 1 micron (about the junction depth for fast low-voltage bipolars) is 11.4 nanoseconds.
The thermal timeconstant for silicon of size 10 microns (about the junction depth for high-voltage bipolars) is 1.14 microSeconds.
Pulses longer than 1.14 microSeconds will cause serious heating problems, because the thermal mass will not absorb the energy, and the heat generated in the collector will flow a few microns into the emitter-base region and cause thermal runaway, a positive-feedback behavior.
The default silicon wafer thickness is 300 microns; these wafers are often thinned (the back side is ground down) to 100 microns to fit into very thin packages. The thermal time constant of 100 microns is yet another 100X slower, to 114 microSeconds.
The metal plate (flag) under the silicon have about the same thermal properties as silicon, and that gets you to about 1 millisecond of survival time.
Forward(Reverse) Safe Operating Area. The first one relates to power dissipation, so the diagonal (contour) lines will be ambient temperatures; stay in the lower left area. The second is for reverse breakdown, and the contours are E-B voltage. Read the rest of the chapter for details, these appear to be example charts rather than specs.