0
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Assume I have the following constraints file which specifies only one single input:

set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { Switch }];

And the following top file which also lists input A and output B in it's port specification:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test11 is
port (
    Switch      : in std_logic;
    A           : in std_logic;
    B           : out std_logic
);
end test11;

architecture Behavioral of test11 is
begin
    B <= A xor Switch;
end Behavioral;

This compiles just fine.

Are A and B assigned to some random pins? Are they tied to '0' or '1'?

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  • \$\begingroup\$ You can explicitly check what was actually generated by looking into "FPGA Editor". The signal are not tied to anything, output is tied to whatever internal logic is, and inputs are tied to IO ports, and needs to be defined externally. \$\endgroup\$ – Ale..chenski Dec 10 '18 at 18:31
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If you did not explicitly assign them in your .UCF file they are "randomly" assigned. You should see B assigned to an output (as the output of your logic), and A and switch are assigned to inputs. Open your PAR report to see where they were assigned. Create a UCF file to constrain them, and add it to your PAR phase. There are other constraints that belong in the UCF as well. IO standard, slew rate, direction, setup/hold times, etc.

If you aren't familiar with a .UCF file syntax, look in the /docs of your install, or online for the "constraints guide"

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  • 1
    \$\begingroup\$ Viviado uses .XDC files instead of .UCF (which was used by ISE). The XDC files for the most part follow the Synopsys Design Constraints (SDC) format \$\endgroup\$ – ks0ze Dec 11 '18 at 20:53
  • \$\begingroup\$ Yep, thanks for the clarification. I've been on the verification side (mostly) since Vivado came out. SDC format is much better than the UCF syntax. \$\endgroup\$ – CapnJJ Dec 11 '18 at 21:25

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