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I'm currently doing the fanout for a ~500 Pin FPGA. To keep the layer count of the PCB low, I'd like to lower the clearance/track width in the area of the FPGA in order to route traces between the pads. However, I do not want these low clearances/track widths to be valid for the whole board, to not cause any unecessary trouble for the PCB manufacturer.

Unfortunately, I have no idea how to set up such an area-based rule in Altium 15. If possible, Id love to just create a room and add clearance/width rules for anything in this room, but that seems to not be possible.

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  • \$\begingroup\$ Nevermind, i found it. theres a constraint WithinRoom('roomName'). I didnt know thats a thing cause its not listed in the query builder. \$\endgroup\$ – L. Heinrichs Dec 11 '18 at 11:04
  • \$\begingroup\$ If you find it yourself, please post this as an answer. This may help people finding this post in the future to the right solution. \$\endgroup\$ – Remco Vink Dec 11 '18 at 11:34
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The answer is using the WithinRoom Query, that I did not find in the Query Builder, so I didnt know it exists. To create rules limited to a region, you may

  1. Place a room called e.g. MyRoom, covering the area that you want altered rules in
  2. Create a rule with Query WithinRoom('MyRoom')
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