I'm currently doing the fanout for a ~500 Pin FPGA. To keep the layer count of the PCB low, I'd like to lower the clearance/track width in the area of the FPGA in order to route traces between the pads. However, I do not want these low clearances/track widths to be valid for the whole board, to not cause any unecessary trouble for the PCB manufacturer.
Unfortunately, I have no idea how to set up such an area-based rule in Altium 15. If possible, Id love to just create a room and add clearance/width rules for anything in this room, but that seems to not be possible.