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Could somebody please explain how to find the address space for the RAM, Sensors, Alarm and ROM? :)

The answer is supposed to be

  • ROM: 0000-1FFF
  • RAM: 2000-3FFF
  • Sensors: FFF0 - FFFF
  • Alarm: FFFE
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    \$\begingroup\$ Hint: A chip is selected when CS(bar) is 0. Since it is active low and the chip is then selected. The design is such that this will be true for only 1 chip at a time. Whenever a chip is selected and others aren't, we say we are in its address space. \$\endgroup\$ – ijuneja Dec 11 '18 at 14:06
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    \$\begingroup\$ You have the RAM and ROM swapped, ROM is 0000-1FFF, RAM is 2000-3FFF \$\endgroup\$ – Steve G Dec 11 '18 at 14:19
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    \$\begingroup\$ Nitpicing: the thing on the left side should probably be labeled microprocessor, not microcontroller, because it uses external ROm, RAm and peripherals. \$\endgroup\$ – Wouter van Ooijen Dec 11 '18 at 18:39
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Look at which bits of the address (A0...A15) have to be in which state to enable each memory-mapped chip. Notice that address lines which are not connected to the CS line are don't cares when it comes to selecting the chip, i.e. some bits (hardwired) select the chip, the other bits allow to access addresses in that chip, making up the address range/space of that chip. For the alarm, for instance, since all address bits are hardwired to the alarm's CS, there's only one single address which is used to access the alarm. For the RAM, only three address lines are used to select RAM, leaving (16-3)=14 bits for adresses in RAM i.e. 2^14=16k addresses.

Also worth noting: In general, no two chips may be selected by the same combination of relevant address bits, i.e. address spaces may never overlap. (Unless in certain special cases where other means are designed-in to prevent two chips writing to the data bus at the same time, e.g. if one chip is read-only and the other is write-only so that whenever one of them is connected to the bus the other one is not.)

Because the CS inputs of the chips are inverted inputs (/CS), i.e. active low, it may be helpful to regard them as "chip disable" lines. For every address, all but one chip must be thus disabled.

In the example, RAM is hence disabled for any address where A15=1 or A14=1 or A13=0, in binary 0b110xxxxxxxxxxxxx, the inverse of that bit pattern enables the RAM; so every address from 0b001xxxxxxxxxxxxx will access RAM, which in hexadecimal is 0x2000 (0b0010000000000000) up to 0x3FFF (0b0011111111111111).

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    \$\begingroup\$ Non-overlapping spaces would be great, and should be designed in. This is a poor example of that, since sensors and alarm are both selected at 0xFFFE. This is acceptable, though, if one is read-only and the other is write-only, or if the conflict is resolved otherwise. \$\endgroup\$ – Cristobol Polychronopolis Dec 11 '18 at 15:03
  • \$\begingroup\$ "No two chips may be selected..." Well, they might be, if the hardware designer wasn't on their toes. Or if they have valid reasons, as @CristobolPolychronopolis points out. \$\endgroup\$ – TimWescott Dec 11 '18 at 16:20
  • \$\begingroup\$ Thanks for pointing this out. Indeed it looks like in the OP the intention was that the "sensors" would be read-only (input) and the "alarm" write-only (output); then it's probably also no coincidence that the sensors have a "/R" and the alarm has a "W" label on the pin. \$\endgroup\$ – JimmyB Dec 11 '18 at 17:09

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