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My computer organization and architecture claims that with 1-bit predictor, there are 2 mispredicts.

The first miss is when mistaken on last iteration of inner loop.

The second one is as not taken on first iteration of inner loop next time around.

I can't get why the second one occurred.

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A mispredict occurs when the a descision is not the same as the previous decision (at that particular statement).

For the anaysis only the intter loop (contr9lled by the first BEQ) is relevant.

The inner loop ends with a 'BEQ inner' not taken.

  • The inner loop starts with a 'BEQ inner' taken. That's different from the previous decision, hence a mispredict.

  • (as noted above) The inner loop ends with a 'BEQ inner' not taken. That's different from the previous decsision, hence a mispredict.

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  • \$\begingroup\$ what about the outer loop, when it first came out of the inner loop, it would be made "taken" again. \$\endgroup\$ – Tki Lio Dec 11 '18 at 17:59
  • \$\begingroup\$ Yes, but so what? A 1-bit branch predictor is effectively 1 bit per individual brach instruction so the two braches doen't interfer. \$\endgroup\$ – Wouter van Ooijen Dec 11 '18 at 18:33
  • \$\begingroup\$ You mean there are 2 separate bits for 2 loops? \$\endgroup\$ – Tki Lio Dec 12 '18 at 3:10
  • \$\begingroup\$ There are N separate bits for N different addresses, selected by (for instance) the lower bits of the intrsuction address. \$\endgroup\$ – Wouter van Ooijen Dec 12 '18 at 7:03

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