# Clock frequency of FPGA circuit and 4-bit counter [closed]

I have implemented a 4 bit counter using HDL. Now I have downloaded the code to an FPGA kit with a 50 Mhz oscillator. This means that the clock period will be equal to 0.02 microseconds and consequently we will not recognize the counting process if the 4-bit output will be implemented on a 4 LEDs. So to solve this problem, I have changed the code so that the counter output signal will be equal to 28 bit and then I have coupled the 4 LEDs with the 4 most significant bits (24,25,26 and 27) so that I can recognize the counter as now the counter will count on 28 output bits instead of just 4 bits. Now, I need to prove these using equations or in other words, I need to quantify this effect to prove that this will work and the counting process will be notified by users of FPGA in my presentation for this small project. So how do I quantify it?

• Quantifying and proving are two very different things. You might start by either trying it or simulating it. You could try it with a shorter register if that length intended for human-scale output is a bit long to simulate. Once you have a reliable model of how a short counter behaves (in particular, that it counts at all, and that there's no extra divide-by-two somewhere you overlooked) extended it to a longer one should be quite simple. Dec 11, 2018 at 21:08

as you know if you have 4bit_counter, you can see the fourth bit(most left bit) of this counter becomes one after counting eight rising_edge_clock, it means 2^3 ;

so in your case, 24th bit becomes one after finishing (2^23)-1 counts and since the clock period is 0.02 milliseconds it takes (2^23)*0.02 milliseconds. this rule is applicable to the remaining three LEDs of course:

25th bit : (2^24)0.02 ms ; 26th bit : (2^25)0.02 ms ; 27th bit : (2^26)0.02 ms ;