Multiple small vias will make little or no difference to the signals at the frequencies you are working at.
In the old days, where drill holes were a penny each, you carefully counted holes for cost reasons but that is rare these days as machines are much better. Often this fact is misremembered as a design rule.
Consider a bit of source impedance matching (i.e. a series resistor at the driving end) of your fast signals to reduce the effect of reflected signal edges.
Consider loosely matching the trace impedance to this source impedance.
e.g. If the driver drives 0V out at 10mA with an output voltage of 0.1V then it has an output impedance of 10 Ohms. Add another series 39 Ohms to make it 49 Ohms, then make the trace 50 Ohms along it's length as best you can. If it's 45 or 55 (or perhaps further out), it will make little difference.
The trace capacitance coupled with this series resistance will also reduce rise and fall times, this is not always a bad thing.
Attenuation of the 'high frequency' components of the clock is actually desireable to a small extent, a needlessly very fast edge is the worst case for EMC emissions.
The use of back drilling and microvias can be used to reduce the parasitics of vias, but are really not necessary for the frequencies used in JTAG or even 100 Base Ethernet. MDIO is very slow so of little concern.
EMC issues aside, if the clock overshoots or rings a bit, so long as the ringing is less than half a clock period in width and less than 20% of the signal amplitude then it should have little or no effect on circuit performance.
Source impedance control has the effect of damping any ringing caused by mismatch and trace (or pin) parasitics.
Remember, you rarely have to worry about EMC for JTAG as it's not a 'normal function'. (But this does not mean you should avoid source impedance control)
For your 100 Base Ethernet, yes I would be careful to limit the number of vias, though less due to their capacitance, more due to the impedance discontinuity inevitable each time you via a differential pair.
As a suggestion; I've had a lot of success with differential co-planar waveguide (DCPW) with Ethernet from 100MHz up to 10GHz. If you can do it all the way from PHY pin to connector it needs no vias at all. I would recommend stapling/stitching the plane along the guide.
It's easier to add a few 0402 (or smaller) low value resistor pads and fit 0R when you find you don't need them than retro fit them under pins later. You can always cost reduce them out in the next board spin.