We are designing PCB with multiple ICs (up to 10 ICs). Each IC has MDIO and JTAG interface. The board has two signal layers, one power layer and GND plane. We have to route JTAG and MDIO lines to each IC, so the tracks become pretty long and what is the main point of concern - there are too many vias between layers.

For example while I was routing JTAG TCK track to the last IC, I had to add 8 vias. As far us I understand each via adds some inductance to the line, so the high frequency components of the clock may be attenuated. Should we consider for the number of vias and trace length while routing JTAG and MDIO pins? And also how the number of vias influences the wave impedance?

Is it a good practice to route high speed nets like 100BASE-TX diff pairs using some vias? Or we must add extra layers to keep the number of through hole vias less than two?

  • \$\begingroup\$ What is the extra cost to get the PCB made with more layers? You need to prove the concept first so do everything you can to achieve that. Then, if you think your cost sensitivity demands fewer layers then try it and see if you still get reliable operation but, my main concern (when developing a PCB) is to prove the concept first and giving yourself the best possible chance means using more layers. \$\endgroup\$ – Andy aka Dec 12 '18 at 10:59
  • 1
    \$\begingroup\$ Thank you for response!) But what is disadvantage of using multiple vias instead of using extra layers? \$\endgroup\$ – Andy Dec 12 '18 at 13:07
  • 1
    \$\begingroup\$ @Andy first of all, it might simply be impossible to bring out all pads e.g. from a BGA component with too few layers, at all; not enough space, and no dimenstion to escape to. You already mentioned the inductance of vias, that's a good reason. Whether or not this works is hard to say. What is not hard to say is that 8 vias in a single signal line sounds like too many for a relatively benign board (10 ICs only), and chances are a redesign of the component placements and rotations, as well as better premediated routing might greatly reduce this. \$\endgroup\$ – Marcus Müller Dec 12 '18 at 13:32

If your concern that adding via adds inductance to the line, don't forget the trace itself is an inductor, and capacitor.

Via wouldn't significantly increase your trace inductance if this one is already long.

How "long" is long ? I've got designs with JTAG over pretty long traces, like 10cm. And even the JTAG often have some extra wires from the connector.

You can increase the trace width in order to reduce the resistance and that will reduce the negative effect of the inductance (It won't reduce the inductance, but the "resistance" of the line that is in serie with the inductance).

For high speed, via won't be too much of a concern, it is even sometimes necessary especially if you have through hole connectors, you have to avoid rigging down the pin of the connector and you need to route from the bottom of the pcb, like in USB-C.


Multiple small vias will make little or no difference to the signals at the frequencies you are working at.

In the old days, where drill holes were a penny each, you carefully counted holes for cost reasons but that is rare these days as machines are much better. Often this fact is misremembered as a design rule.

Consider a bit of source impedance matching (i.e. a series resistor at the driving end) of your fast signals to reduce the effect of reflected signal edges.

Consider loosely matching the trace impedance to this source impedance.

e.g. If the driver drives 0V out at 10mA with an output voltage of 0.1V then it has an output impedance of 10 Ohms. Add another series 39 Ohms to make it 49 Ohms, then make the trace 50 Ohms along it's length as best you can. If it's 45 or 55 (or perhaps further out), it will make little difference.

The trace capacitance coupled with this series resistance will also reduce rise and fall times, this is not always a bad thing.

Attenuation of the 'high frequency' components of the clock is actually desireable to a small extent, a needlessly very fast edge is the worst case for EMC emissions.

The use of back drilling and microvias can be used to reduce the parasitics of vias, but are really not necessary for the frequencies used in JTAG or even 100 Base Ethernet. MDIO is very slow so of little concern.

EMC issues aside, if the clock overshoots or rings a bit, so long as the ringing is less than half a clock period in width and less than 20% of the signal amplitude then it should have little or no effect on circuit performance.

Source impedance control has the effect of damping any ringing caused by mismatch and trace (or pin) parasitics.

Remember, you rarely have to worry about EMC for JTAG as it's not a 'normal function'. (But this does not mean you should avoid source impedance control)

For your 100 Base Ethernet, yes I would be careful to limit the number of vias, though less due to their capacitance, more due to the impedance discontinuity inevitable each time you via a differential pair.

As a suggestion; I've had a lot of success with differential co-planar waveguide (DCPW) with Ethernet from 100MHz up to 10GHz. If you can do it all the way from PHY pin to connector it needs no vias at all. I would recommend stapling/stitching the plane along the guide.

It's easier to add a few 0402 (or smaller) low value resistor pads and fit 0R when you find you don't need them than retro fit them under pins later. You can always cost reduce them out in the next board spin.

  • \$\begingroup\$ Thank you for the response!) It's a great answer!) \$\endgroup\$ – Andy Dec 13 '18 at 5:44

I would route the critical signals first, and then the slowly changing or basically static signals (example: Reset) last.

Back when I was creating high-chip count (80+), SMD designs, that were then routed on 16 layer boards, we had to come up with lists to give to the board layout folks of which signals were critical, which had to be given priority with minimal vias, where the parts were to be placed for access to connectors, trace widths to be used, where the decoupling caps had to go, etc.

When they were done, we reviewed the routing, and the computer analysis reports on them. Runs with lots of vias were reviewed, runs that were really long were reviewed, and if we as the engineer were not happy with the routing then those signals were redone.

When I create smaller boards now, mainly for use with Arduino circuits, I do the same, and try to minimize vias and layer changes as much as I can for cleaner signal runs, and to help with breaking up the ground planes. Adding GND vias to connect top & bottom GND areas can help with that.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.