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I recently took an undergrad computer architecture course and had a question about using multiple cores after seeing how dense the field of research is. I am thinking about a general idea of how many cores can be used adaptively to accomplish both very parallelizable and not-really parallelizable tasks without relying on the OS too much.

So my question is: Given they can share the same data and I/O buses and the same registers, could there be an architectural design where multiple processing units go through one set of instructions by switching between units?

For example, assume you had two processing units being fed two different clock signals 180 degrees out of phase. Could one unit process an instruction during its clock high and then the second unit process the next instruction during its clock high (the first unit's clock low)? So unit 1 would do every odd instruction and unit 2 every even.

Here's a rough diagram of what I mean by the two clocks being used together. Example of two clocks being used sequentially

Is this doable, or am I missing something? I couldn't really find much about this on the web or SE since I'm not really sure what keywords to use for this question.

I'm basing all of this on my understanding of the LC-3 architecture, though it's a little outdated and may not reflect modern-day architectures.

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    \$\begingroup\$ How would you resolve data dependencies? E.g. instruction 2 depends on the results of instruction 1? \$\endgroup\$ – tangrs Dec 13 '18 at 4:56
  • \$\begingroup\$ Wikipedia: Superscalar processor - we have those in our PCs since the mid-90's. \$\endgroup\$ – Turbo J Dec 13 '18 at 11:39
  • \$\begingroup\$ Why are your processors idle 50% of the time to begin with? \$\endgroup\$ – Dave Tweed Dec 13 '18 at 12:52
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Given they can share the same data and I/O buses and the same registers, could there be an architectural design where multiple processing units go through one set of instructions

This is generally known as "superscalar" design, and is used by almost all modern processors.

As the others have hinted at, the key problem is data dependencies; the cores need to be executing instructions that don't depend on each other's results.

Could one unit process an instruction during its clock high and then the second unit process the next instruction during its clock high

Negative-edge clocking can be done, but it's a very unpopular technique, because in almost all cases you can replace it with a clock twice as fast and do operations on positive edges only, introducing pipeline delays where the circuitry can't keep up. The one common case it's used is DDR SDRAM.

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It all works fine until the blue core needs a data value at the start of its instruction that the red core hasn't finished producing yet.

You get much the same sort of difficulty with a pipelined single core, where the data value from one instruction is required for the next. The deeper the pipeline, the more cycles are lost in the stall while the second instruction waits for the results of the first.

A mitigation for the second problem, and it would also be applicable to the first if you ever tried to build it, is micro-threading. If the data is not available yet, work on something else for a while.

Unfortunately, this requires multiple independent processes to be offered to the processor. This is perhaps what's behind a resurgence in the popularity of a pure functional programming style, where side-effect-free functions can be run in parallel automatically without human prodding.

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