I created the above circuit. There is essentially a switch that is normally high. I press a button. Using a NTE4049T hex inverter, I create a low to high edge transition. This provides the clk input to a 74HCT175 D flip flop. Everything is run at TTL, 5 Volts. The output of the D flip flop is fed into another NTE4049T hex inverter to then feed the D input of the flip flop.
Ideally, when the button is pressed, I would create a toggle of the Q output line.
This does not happen. In fact, there is some oscillation at the signal output, but no finite transition of state.
I realize that this is a result of continuous toggling/bad design. How is this problem solved? If I chained the output of the D flip flop into another flip flop, also clocked to the same edge, to then generate an inverted output for the first flip flop, would that solve the state oscillations? Could I pass the output through a series of buffers to create a time delay?
The first pic is the waveform of the switch with the rc network. There is an instaneous drop when the switch is depressed. This drop, through an inverter, is what causes my clk signal to go high.
The pictures below show a high level view of the Q signal output as well as a zoomed in image at the tail where the Q signal then goes back low. I believe in this tail section the capacitor is charging. I'm not sure why it would cause the d flip flop to again trigger. There should not be a rising edge?
The light blue line represents the clock transition signal on the flip flop. The yellow line represents the D signal being fed into the flip flop. The dark blue line represents the Q signal of the flip flop, just before going into the inverter. The inverted output will again feed the flip flop a D.
How is a problem like this solved in practice if I cannot solve it in the above design? Thanks