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I have a question regarding a circuit providing low current capacity voltage for device powering, that goes down from a lot higher voltage:

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How does it exactly work? I understand that the Q1 gate is biased at 5.6 V no matter what is the voltage level on the Q1 drain (because of the zener diode). But how come there is around 4V at Q1 source? The Vgs of the Q1 is around 2.5 V (2N7002-7-F). The voltage at Q1 drain can vary and the voltage at source stays around 4V. This schematics is a part of circuit found in the BQ34110 datasheet. I would appreciate all hints.

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Vgs threshold voltage is ranging from 1V to 2.5V according to the datasheet. The source voltage is regulated to Vg - Vgsth --> 5.6V-1 to 2.5V. Seems like your Vgsth is around 1.6V. For better understanding consider you have a resistive load on your mosfets source. When the current through the load rises so does the source voltage. This leads to an reduces Vgs which results in an higher Rdson of the mosfet and therefore a smaller current, which again results in a higher Vgs voltage.

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  • \$\begingroup\$ Very good explanation, thank you. This means that innorder to have a desired voltage level on the source of the q1, the Vgs threshold has to be picked very carefully? \$\endgroup\$ – Bremen Dec 14 '18 at 8:19
  • \$\begingroup\$ That Vgs will change somewhat over temperature and the current through the NMOS so "picking it carefully" doesn't help much. It all depends on how accurate/stable you need the lower supply voltage to be. Use an NPN instead of a PMOS to get a bit more stable voltage. Use a voltage regulator to get even better stability. \$\endgroup\$ – Bimpelrekkie Dec 14 '18 at 8:30
  • \$\begingroup\$ I would use a voltage regulator, but the voltage I intend to lower to around 4 V is around 400 V. The load current with the lower voltage is very slight though. \$\endgroup\$ – Bremen Dec 14 '18 at 12:07

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