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According to a Junction Field Effect Transistor (JFET) article in ElectronicsTutorial, the voltage across the source resistance is equal to 1/4 the supply voltage applied to the drain/gate for a class "A" amplifier. Quoting from the article:

This common source (CS) amplifier circuit is biased in class “A” mode by the voltage divider network formed by resistors R1 and R2. The voltage across the Source resistor RS is generally set to be about one quarter of VDD, ( VDD /4 ) but can be any reasonable value.

I set out to verify this equation by using it in a question that I was attempting to solve, a simple DC biasing equivalent voltage-divider JFET circuit with 2N3819 as the JFET component for my circuit.

Simple JFET Circuit

Assuming that:

  • R2 = 150k Ohms
  • ID (Drain Current) = 3mA
  • IDSS (Saturated Drain Current) = 10mA
  • VDD (Supply voltage for DC bias) = 20V
  • VDS (Drain-source voltage) = 7V
  • VGS (Gate-source voltage) = -3V

I set out to find the unsolved resistance values and the required voltage values. Based on using VS = VDD/4 and other equations like Shockley's Equation and the KVL equations concerning the gate/gate-source/drain-source voltage:

  • Vgs = Vg - Vs
  • Vds = Vdd - IdRd - IdRs
  • Shockley's Equation
  • Voltage divider rule for finding the gate voltage, Vg

I was able to find the calculated voltage values (which will be used to compare with the simulated results):

  • Vg = 3.643V
  • Vgs = -1.357V
  • Vs = 5V
  • Vd (drain voltage) = 8V

The calculated resistance values were:

  • R1 = 673459.2173 Ohms
  • RS = 1666.67 Ohms
  • RD = 2666.67 Ohms

Plugging the calculated resistance values into the simulation gives me:

Simulation results

It seems that VS = VDD/4 is correct, albeit with slight differences in the value between the calculated and simulated results:

  • Vg (simulated) = 3.643V [matches calculated value]
  • Vs (simulated) = 5.117V [differs from calculated value with difference of 0.117V]
  • Vgs = -1.474V [differs from calculated value with difference of 0.117V]
  • Vd = 8.19V [differs from calculated value with difference of 0.19V]
  • Id = 3.07 mA [differs from original value with difference of 0.7mA]

Now that I have verified that the equation is actually correct, I want to ask:

  1. How is the equation VS = VDD/4 derived?
  2. What causes the difference between the simulated and calculated values? Is it because of additional factors (like wire resistance) that the simulation software considers when showing the simulated results?
  3. Is there another way to find the calculated resistance/voltage values without having to use the aforementioned VS equation or the graphical method?

Thanks.

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  • \$\begingroup\$ I am new here, so please let me know I should add, remove or modify something in my post. Thanks. \$\endgroup\$ – gigglydeejay213 Dec 14 '18 at 6:27
  • \$\begingroup\$ At the bottom of your post there are the words "share, edit, flag". If you want to modify your question you can click on the word "edit". \$\endgroup\$ – Martin Rosenau Dec 14 '18 at 6:31
  • \$\begingroup\$ About your first question: The text in the quote says: "... is generally set to be about one quarter of VDD, ( VDD /4 ) but can be any reasonable value." If I understand this correctly, you can also design a circuit in a way that the voltage is VDD/3 or VDD/5 or whatever value. However for some reason it makes sense to use VDD/4 instead of VDD/3 or VDD/5. \$\endgroup\$ – Martin Rosenau Dec 14 '18 at 6:33
  • \$\begingroup\$ @MartinRosenau Thanks for the tip. Also, very interesting observation that I have overlooked. I re-did my calculations based on VDD/(3, 2, 5) and surprisingly there is no difference between using VDD/4 for finding the values based on the circuit. I wonder what circumstance led to this outcome? \$\endgroup\$ – gigglydeejay213 Dec 14 '18 at 6:55
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How is the equation VS = VDD/4 derived?

You need to bias the gate below the source.

And the output amplitude at the drain will only be limited to the difference between Vdd and the bias voltage on the drain.

So you choose your resistors to give you \$V_s \approx V_{dd}/4\$ to roughly maximize the possible output amplitude while allow a reasonable range of input amplitudes.

What causes the difference between the simulated and calculated values? Is it because of additional factors (like wire resistance) that the simulation software considers when showing the simulated results?

The simulator doesn't consider wire resistance.

But it does use a much more complete model for the JFET than whatever you used for pen-and-paper calculations. This is probably the main reason for the difference between the simulation and the calculation.

In fact, you arbitrarily assumed values for ID, VDS, and VGS, so I'm not sure what model for the FET you were using. Generally you should have to do some calculations to get one of these three values after choosing the other two.

Is there another way to find the calculated resistance/voltage values without having to use the aforementioned VS equation or the graphical method?

Practically, you can fire up the simulator and do some parameter sweeps to pretty quickly find appropriate resistor values for this kind of circuit.

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    \$\begingroup\$ And, to add to this answer (for the OP), if you intended to bias the source at only 1 or 2 volts above ground you might find that it is unachievable without resorting to a source resistor that is unfeasibly high in value. \$\endgroup\$ – Andy aka Dec 14 '18 at 9:04

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