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I have a N-MOSFET as power switch like this:

enter image description here

I want to add a fuse on the power line but I have few capacitors on the across the load and I am worried that the inrush current might blow the fuse off. How can I limit the inrush current here? I saw that for P-channel one can add capacitor across drain and gate. I am not sure if this works for N-ch MOSFET as well.

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  • \$\begingroup\$ where is that fuse in your diagram? \$\endgroup\$ – Marcus Müller Dec 14 '18 at 12:43
  • \$\begingroup\$ whats wrong with the pmos version? \$\endgroup\$ – Jogitech Dec 14 '18 at 12:45
  • \$\begingroup\$ Nothing wrong with pmos but my VDD will be On only if the FET is on. For pmos I need the VDD to be on all the time. \$\endgroup\$ – zud Dec 14 '18 at 13:14
  • \$\begingroup\$ @MarcusMüller The fuse will be between the VDD line and the voltage source. \$\endgroup\$ – zud Dec 14 '18 at 13:15
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    \$\begingroup\$ I am worried that the inrush current might blow the fuse off. Before actually solving this "problem" how are you sure it actually is a problem? Fuses are slow (even the fast ones). I would not try to "fix" this problem before I actually have confirmed that it is a problem. There are still many unknowns, like what capacitors (and what is their ESR), what is the supply (perhaps it has a limited output current: problem solved), and even: what fuse?? You're like the rookie engineer who sees problems everywhere due to lack of experience. \$\endgroup\$ – Bimpelrekkie Dec 14 '18 at 13:18
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With Nmos ist basically the same...cap between gate and source but an additional high side Driver with a high resistance on ist output and a diode in paralell to the resisor.

schematic

simulate this circuit – Schematic created using CircuitLab

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In this case a cap between drain and gate would limit the rate at which Vds decreases (i.e., Vload increases). If limiting that voltage ramp will address your inrush current issue, that's the easy route.

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