I got these timing diagrams (1 ms/Div and 5 V/Div) :
I think that the output Q is inconsistent , shouldn't it look like this instead ? :
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The big problem is that it could be either waveform - the data needs to be setup prior to clocking the 7474 flip flop. It is a positive edge driven device and if you setup data at the instant it receives a positive clock edge then you cannot guarantee what the data is. The fact that your simulator model decides to assume the data is high when the clock rises and is low on the next clock edge is irrelevant because you need to drive the flip flop correctly or you'll get garbage in real life and lies in the simulator.
Setup and hold times for a flip flop: -