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So I am doing a layout for a 4 layer PCB 1 ounce/layer. The Chip supports up to 20A (motor controller driver). The application needs about 12 amps max ( I plan it let it go up to 17A in the event of failure, controller force shutdown at 15A. In theory it should shuts down gracefully instead of just burning the trace out)

If I let it go up to 105 degrees (so 25 + 80) the trace width is 167mil on a single outer layer and 434 on a single inner layer as indicated by https://www.4pcb.com/trace-width-calculator.html

I am going need to separate the grounds between micro-controller and the Motor input (motor is noisy, I can't control that.) I was thinking, should run 85 mil on top and bottom traces, and 217 mil on the 3.3v and GND plane for the return current. (Rest will be poly-filled 3.3v for the power plane and board ground GND plane.)

The two ground planes will be tied together with a ferrite bead. Is there any downside to using 217 mil on both 3.3v and board ground layers? Or should I do a 434 mil on the power layer and leave the ground uniform board ground? Or any other suggestions?

H-bridge

The heavy outline is the chip (not exact same model but similar spec, I cant find an exact one with schematic, this one has more features.) So it goes from VCC -> HSA -> LSB -> GND or VCC -> HSB -> LSA -> GND depending on the direction of the motor. It's two half bridges.

I have no control over the FETs in the chip itself - it’s all built into the driver chip. Remember, the outline itself is a driver chip; I have no control over what is used on the inside. So what I have is battery (Vcc) to the diver, and it gives me outA, outB, gndA, gndB. The PWM isn’t in the wrong place, it just shows it as an input in that diagram. I think the lower FET in that diagram is telling the user how to wire for reverse battery protection. So the current goes from battery -> (into PCB) to chip -> (on pcb) HSA -> (off pcb to) motor -> (on pcb) LSB -> GND (out back to battery.)

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    \$\begingroup\$ NOTE: that tool implements IPC-2221 with regards to current. This is obsolete and has been superseded by IPC-2152 \$\endgroup\$ – JonRB Dec 16 '18 at 13:26
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    \$\begingroup\$ As to your question... the devil is in the detail AND more specifically the path the return currents will take. if you can provide a block sketch as to where you think things will go, comments can be made w.r.t. the natural/lazy return paths \$\endgroup\$ – JonRB Dec 16 '18 at 13:27
  • \$\begingroup\$ @JonRB Its something like imgur.com/a/7jFGUzn , the heavy outline is the chip ( not exact same model but similar spec, I cant find an exact one with schematic , this one have more features) So it goes from VCC -> HSA -> LSB -> GND or VCC -> HSB -> LSA -> GND depending on the direction of the motor. Its two half bridges \$\endgroup\$ – Kevin Dec 16 '18 at 14:12
  • \$\begingroup\$ do you have a layout blockdiagram/schema, this is what will be important. You need to think about return currents. Such layout isn't novel but it is easily compromised but poor understanding. \$\endgroup\$ – JonRB Dec 16 '18 at 14:17
  • \$\begingroup\$ Also you are using all N-types and there doesn't appear to be any suitable means to drive the upper devices gate above Vcc (unless Vcc < 5V-Vth, which I doubt). Also the lower disconnect/pwm FET appears to be upsidedown \$\endgroup\$ – JonRB Dec 16 '18 at 14:18

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