I have a board with a 3.3v MCU (C8051F850 from Silicon Labs in a QSOP-24 package) but whose pins are 5v tolerant. The board is running at 5v and all the relevant GPIO pins from Ports 0 & 1 have 10k external pull-up resistors (in a SIP package) on them. So my question is;

What voltage should i see on the board track on the other side of the pull-ups if i output a logical "1" i.e. 3.3v on a output pin configured as;

a) push-pull ?

b) open-drain ?

Note that i understand that since the board voltage is higher than the MCU's, the pins should be used "active low" but i would like know what happens in the reverse scenarios mentioned above.

  • \$\begingroup\$ This is XY problem. Show exact circuit diagram. \$\endgroup\$ – Anonymous Dec 17 '18 at 9:02
  • \$\begingroup\$ I disagree; this is NOT a "XY problem" and there is no circuit diagram to show. To restate it simply; There is a 10k resistor which has a 5v source on one side and connected to a 3.3v MCU pin on the other side. What happens when the MCU outputs 3.3v under push-pull and open-drain pin configurations? \$\endgroup\$ – RamanathanR Dec 17 '18 at 9:10
  • \$\begingroup\$ (1) Why does the output voltage matter, and (2) why don't you measure it, especially if the voltage level actually does matter? \$\endgroup\$ – Dmitry Grigoryev Dec 17 '18 at 10:15

This is a standard open drain output. The diodes protect against ESD by redirecting ESD to ground or the power supply.

enter image description here

In your case the microcontroller runs on 3V3 but the output pin is 5V tolerant, so the top ESD diode will not be a simple diode which would conduct when Vcc=3.3V and Vout=5V. Rather it will be some form of FET-based protection which will only conduct when the output voltage exceeds some margin above 5V.

When the FET is ON (output logic 0), it will short the output to GND, so output voltage will be close to 0V. Nitpicking, if we have a 10k pullup to 5V and FET RdsON is 20 ohms, then we have a voltage divider and output voltage would be about 10mV. Close enough.

When the FET is OFF (output logic 1), voltage will be determined by the rest of the circuit. In your case, with a pullup to +5V, it will be +5V. Without a pullup, it would be "whatever depending on random amounts of leakage current" which is not desirable.

On a non-5V tolerant pin, the top ESD diode would conduct and short the pullup current to the +3V3 supply, so the output voltage would be 3.3V + one diode drop. The same scenario would occur on your 5V tolerant pin if you wired the pullup to a higher voltage than +5V.

Now for the push-pull, I'll steal an image from this page:

enter image description here

It doesn't show the ESD protection, but it is still there of course.

The "output logic zero" case is the same as above.

However when outputting a logic 1, the top FET is ON which connects the output to Vcc, ie +3V3 in your case. Thus, even with your pullup, the output voltage will be +3V3 and not +5V.

Except... if the micro is in sleep mode, and the components on +3V3 rail only use very little current, it is possible that the current through the pullup will exceed the supply current used by your devices. Since the LDO which delivers +3V3 is most likely not able to sink current, there will be nothing to ensure that +3V3 remains constant, and instead it might rise a bit. This may or may not be a problem, but if you intend to use the deep sleep mode, you should ensure that the current in your pullups to +5V is not enough to raise 3V3...

  • 1
    \$\begingroup\$ Apologies for the late reply but thank you for your response, much appreciated. \$\endgroup\$ – RamanathanR Jun 28 '19 at 16:52

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