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I'm now writing a testbench. In my testbench, I want to read the length of a text file and pass it to another module while instantiating. The idea is like this:

module TB();
integer text_len;

ABC #(.text_len(text_len)) ABC_1(//some input/output arguments here);

task read_text(output integer text_len);
//read text file and get the text length
endtask

initial 
begin
read_text(text_len);
end

endmodule

When I compile it using Questasim, it keeps saying the expression for a parameter actual associated with the parameter name text_len for the module instance ABC_1 must be constant. Does anyone know how to deal with it?

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1 Answer 1

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The problem is module instantiation happens at code elaboration before the simulation of any initial blocks. So you cannot use a variable to override a module parameter.

What you can do is parse the file externally to Verilog and either create a `define definition that you compile your source code with, or Questa allows parameter overrides through the command line (look for the vopt -g/-G switches in the user manual)


The defines.vh file would look like

`define TEXT_LEN 5

And your module file would look like

module TB();
`include "defines.vh"

ABC #(.text_len(`TEXT_LEN)) ABC_1(//some input/output arguments here);
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  • \$\begingroup\$ Thanks for your help. Could you explain a bit more on the first method? I'm still new to verilog... \$\endgroup\$
    – hk56740
    Dec 18, 2018 at 1:33
  • \$\begingroup\$ Edited answer with an example \$\endgroup\$
    – dave_59
    Dec 18, 2018 at 1:47
  • \$\begingroup\$ Also, it might help to explain why you want to do this as there might be a completely different approach, especially if this is for a testbench. \$\endgroup\$
    – dave_59
    Dec 18, 2018 at 2:06
  • \$\begingroup\$ I want to create a checker so that I can check if the data output from a module is correct or not, but at the same I don't want to fix the size of the reg containing the sequence which is for me to check the data so that I can use any sequence for me to do the job. Thanks for your help! \$\endgroup\$
    – hk56740
    Dec 18, 2018 at 11:59
  • \$\begingroup\$ If you are using SystemVerilog, why not use a dynamically sized array instead of trying to fix the size of the data? \$\endgroup\$
    – dave_59
    Dec 18, 2018 at 15:40

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