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I have designed a circuit and it is working. However, I think it is too complicated and can be changed or simplified. I might be missing something. I am finding hard to create a 1 second delay.

A locomotive has to run, without attention, backwards and forwards along a length of track. At each end it is to stop for about a second before starting in the reverse direction. light dependent resistors (LDR) are used as sensors and they are under the track. The H-bridge has two logic inputs, X and Y, to control the polarity of the track; X high Y low makes the engine move in one direction, X low Y high makes it move the other way. X and Y in the same state disconnect the supply from the track and stops the engine.

I have access to:

  • 4016 quad bilateral switch
  • 4027 dual J-K master/slave flip-flop
  • 4093 quad 2-input Schmitt NAND
  • 4520 dual 4-bit up counter
  • 4538 dual re-triggable monostable
  • DG211 and DG212 quad analogue switch
  • 555 timer

circuit diagram

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    \$\begingroup\$ No real need on iNAND nverters on output of SR flip-flop. You may have to flip X & Y inputs. \$\endgroup\$ Dec 17 '18 at 16:56
  • \$\begingroup\$ Or R & S inputs to NANDs. \$\endgroup\$ Dec 17 '18 at 17:07
  • \$\begingroup\$ If you explain how the LDR sensors are integrated in the circuit or explain the operation of the circuit, it could be made simpler. Especially with the 555 timer or 4538 available. Part number for LDR sensor. \$\endgroup\$ Dec 17 '18 at 17:12
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    \$\begingroup\$ Any remotely sensible implementation of this today would use a cheap microcontroller and drop the bill of materials to just the chip, regulator, and capacitors - you could do this whole thing with an ATtiny85 or a mini Arduino. Mixing logic and timers is going to be physically large, hard to get right, and inflexible. MCUs are extremely common in the model railroad hobby for precisely these kinds of reasons. You may also want to consider an modulated IR reflectance sensor or a reed switch and magnet under the train. \$\endgroup\$ Dec 17 '18 at 18:56
  • \$\begingroup\$ Disagree with Chris. Your answer assumes the OP has a firmware development system and device programmer up and running. Even with all of that already in place, a circuit to do this job can be built from scratch in the time it takes just to think about how to configure the GPIO pins and block out the code. \$\endgroup\$
    – AnalogKid
    Jan 31 at 21:15
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That actually looks pretty good, except that you need to add reference designators to your schematic so that we can talk about it.

The main improvement you could make would be to replace your timer circuit (in the bottom center) with one half of a dual monostable.

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  • \$\begingroup\$ Thank you for your answer! Do you mind explaining more about the one half of a dual monostable ? \$\endgroup\$
    – Neon Star
    Dec 17 '18 at 16:48
  • \$\begingroup\$ Have you read the datasheet? \$\endgroup\$
    – Dave Tweed
    Dec 17 '18 at 16:51
  • \$\begingroup\$ Two things. The comparator inputs are relatively slow edges out of the LDR's, so they probably will produce a noise burst that will re-trigger the monostable and stop the train as it is leaving the station. Also, with the components shown the voltage on the timing capacitor at one minute will be outside the common mode operating range of the 2902. \$\endgroup\$
    – AnalogKid
    Jan 31 at 15:26
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You wanted a more simple solution - ? OK, try this.

enter image description here

The LDR's now are tied to Vcc. Their logic polarity is reversed from my first schematic because there no longer are inverting gates between them and the ff inputs.

U1 is eliminated. The LDR's now drive the ff directly. This eliminates the need for noise filter capacitors, because the LDR's no longer drive the monostable directly (where re-triggering was an issue), and noise or re-triggers at the ff inputs don't matter; once the ff changes state, it stays there no matter what happens on the triggered input, until the other input is triggered.

The ff inputs now are doing double-duty as Schmitt trigger voltage comparators. The comparison voltage level is fixed within the chip, and can vary from one part to the next (see the datasheet for the exact part you have), which is why the LDR bias resistors are adjustable.

The timer is basically the same as before, but the logic polarity (and hence the charging direction) is reversed. This is because there no longer is an inverter between the timing components and the bridge driver signal gates (U2C and U2D). Two timing capacitors, one for each ff state-change, are diode-ORed into one timing resistor, R5. I show R5 as 715 K because 715.96 K is the calculated value based on the original CD4093 datasheet. But again, Schmitt transition levels vary from one manufacturer to the next. If you want to tune the circuit delay period, try a 470K fixed and 500K pot in series to find the correct resistor value for your part.

I show the timing capacitors as non-electrolytic, mainly because I have a bunch of 2.2 uF ceramics. If you use an electrolytic, the anode (+ end) goes toward the diodes. C3 is the power supply decoupling cap for U2. It can be the same as the timing caps.

NOTE: No 555's were harmed in the creation of this design.

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There are two problems with the design, the monostable and the LDR comparators. Plus, some other thoughts ...

  1. In your X-Y table, if the 00 and 11 states truly are equal, then the NAND gate inverters after the NAND gates between the ff and the H driver (Reference Designators - !) are not needed.

  2. I agree with Dave, the monostable part is overly complicated. But separate from that, it won't work. And it will be finicky to adjust because the timing cap must be charged up to over 95% of Vcc to hit 1 minute. But the problem is that the max cap voltage is outside the 2902's input common mode operating range. For this circuit to work the opamp would have to have "rail-to-rail" inputs.

Better to either build a monostable out of two 4093 NAND gates (my preference) or commit to adding another component type to the design, the 4538 monostable. The datasheet says it's output pulse width range includes infinity, but your requirement is a bit shorter than that. The thing to watch is the ratio between the capacitor charging current near the end of the cycle (when it is at its lowest value) and the timing pin (2 or 14) input current. Take the max. value at 25 degree C and double it. You want your min. charging current to be at least 10 times that to reduce it as a source of error and variability (the input current is very temperature dependent).

  1. The comparators after the LDR's do not have hysteresis. This is not a problem for the inputs to the ff, but it is for the inputs to the monostable. As the train moves out, there probably will be a noise burst out of the comparator that will re-trigger the monostable. To prevent this, each comparator must have some positive feedback, called a Schmitt Trigger circuit.

  2. OR, Here's a thought - if you replace the fixed resistors that bias the LDR's with trim pots, then the 2902's acting as comparators can be replaced with 4093 Schmitt gates. And if the ff is built out of 4093 gates, you don't need anything between the LDRs and the ff inputs. This eliminates the 2902 part type from the design, and solves the noise burst problem.

In short - If #1 is correct, the entire circuit can be built with 6 to 8 4093 NAND gates (two chips) plus the bridge driver.

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Here is an all-4093 design. Now that I see this, another version is possible with only 4 gates.

enter image description here

Ci and C2 are noise filters to clean up the slow edges from the LDR's. U1A and U1B act as comparators, turning the LDR ramps into crisp edges. U2A and U2B form the set-reset flipflop. U1C acts as an inverted input OR gate. When either input goes low, the output goes high, pulling both ends of C3 up to Vcc and forcing the output of U1D to go low, disabling the bridge driver signals. C3 charges through R5, and eventually, the voltage across R5 is low enough that U2B changes state, letting the flipflop signals through to the bridge.

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