# SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2.

I know this is a kind of asynchronous scenario and the traditional method is the use of 2 FFs or an asynchronous FIFO to synchronize the data. However, since these two clocks have a fixed phase difference, so is it possible to synchronize the data JUST with SDC constraints? If it is possible, how to set the SDC?

Since we know the phase relation, those clocks are synchronous. The only thing we need to do is telling this relation to the synthesis/STA tool.

create_generated_clock -source clk1 -edges {2 3 4} -combinational [get_pins pll/clk2]


I would use the -edges option to define the phase. The following waveform explains the edges. Basically clk2 rises at the 2nd edge of clk1, falls at the 3rd edge and rises again at the 4th edge.

edge    1    2    3    4    5    6
____      ____      ____
|    |    |    |    |    |
clk1    |    |    |    |    |    |
____|    |____|    |____|    |____
____      ____      ____
|    |    |    |    |    |
clk2         |    |    |    |    |    |
____|    |____|    |____|    |____


The 1-bit data has a half clock cycle to arrive the target FF. By the help of our constraint, the tool will perform setup/hold timing checks accordingly.

• But I think if we constraint clk1, clk2 constraints will be auto generated cz its from PLL. – Mitu Raj Apr 16 at 6:48
• @MituRaj Some tools in some cases propagate clk1 as it is. I wouldn't rely on the tool. – ahmedus Apr 16 at 9:28