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I'm facing problem when reading data register. The SPI communication works perfect, all the registers can be write/read. The data register show -1 (which in datasheet indicates that there is a problem in Vref, checked with setting REF_DET bit and reading STATUS register which shows 0x60).

I'm using adc in BIPOLAR MODE, the steps performed to initialize adc are:

  1. send 0x000A to mode reg.( this sets adc in continuous mode with 16.7 Hz update rate).
  2. send 0x0030 to conf. reg.( this sets adc in bipolar, Gain 1, reference detect ON, BUFFER ON, Channel to 1 ie AIN1+ and AIN1-.
  3. send 0x60 to IO reg. to check p1 and p2 are working.

Please advice why is this happening am I giving wrong Vref, but the datasheet show Vref can be in between 0.1-AVdd and for this I can read upto +-AVdd-100mV (BUFF ON). Please see attached image for reference. I'm trying this CKT from a week now, monitoring Vdd mode works gives some integer value and STATUS reg. shows 4 in this case.

enter image description here

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  • \$\begingroup\$ Have you tried with gain == 1 or higher? I am curious if gain == 0 can work. A lot of references in the datasheet mention a gain from 1 to 128 and the datacode is a multiplication with gain (multiplication with 0 in your case) \$\endgroup\$
    – Eggi
    Commented Dec 18, 2018 at 8:30
  • \$\begingroup\$ sir, setting gain 0 means i set g2-g0 bits to '0' which is equals to gain 1 as in datasheet \$\endgroup\$
    – EEMuks
    Commented Dec 18, 2018 at 8:44

1 Answer 1

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It does sound like Vref is out-of-bounds, or shorted.

Can you measure Vref, directly on the pins Vref+ to Vref-, and also from Vref+ to GND, and then Vref- to GND?

This feels like a PCB error to me.

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  • \$\begingroup\$ It was silly mistake while designing PCB, misplaced pin 9 with 10. So the 5v was going to Vref(-) rather than Vref(+) pin. thanks to Mr. Chris Knudsen for pointing out the problem. \$\endgroup\$
    – EEMuks
    Commented Dec 19, 2018 at 7:49
  • \$\begingroup\$ @the_mighty420 please make sure you mark your question answered. \$\endgroup\$
    – jsolarski
    Commented Dec 19, 2018 at 18:18

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