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I am creating footprint for Amphenol's SD Card Connector in Altium Designer 17. The datasheet shows Pattern Prohibited Area on Page 2. I am assuming there shouldn't be any trace or unmasked via or trace under that area.

In my design, I need to run few traces covered by solder mask in that area. Also, I might be having some vias in that area. For DRC checking, I want to add keepout area in that pattern prohibited area.

Will keepout in my Top Solder Mask layer prohibit any unmasked via in that region? By this, I should be able to run any trace or via covered by solder mask in that area.

If not, what is the right way to achieve it?

My footprint is over here:

enter image description here

enter image description here

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    \$\begingroup\$ FYI, solder-mask is not intended as an insulator. Using it as such runs the risk of having A BAD TIME. You really should not rely on solder-mask for this purpose. \$\endgroup\$ – Chris Knudsen Dec 18 '18 at 16:16
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When a datasheet recommends not having any pattern under a component, that means any pattern (pad, track, via, etc) on that layer, regardless of whether or not it is coated with soldermask. Soldermask can easily scrape off and cause a failure that will be very difficult to track down. When it says "pattern prohibited area", don't put anything in that area. You will need to find an alternative, either running tracks on an internal layer or on the opposite layer.

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  • \$\begingroup\$ Got it. I will avoid any copper in that area. Just for information. How to avoid soldermask in a particular area? Can it be done with keepouts? \$\endgroup\$ – abhiarora Dec 19 '18 at 4:47
  • \$\begingroup\$ You don't necessarily need to avoid soldermask, unless the datasheet specifically tells you to. If it does (which is very rare), you can switch to the Soldermask layer and draw a Fill in the area you want to be left open. \$\endgroup\$ – DerStrom8 Dec 19 '18 at 11:43
  • \$\begingroup\$ I understood that I should have keepout of copper. But my question is how can I add a fill (in solder mask with keepout attribute) in footprint so that in Layout, whenever there is any Fill (solder mask layer) in that area. My DRC will warn me. In Altium, Solder Mask Layers are negative. That means, any Fill in the Solder Mask layer will have that area removed in actual solder mask. \$\endgroup\$ – abhiarora Dec 21 '18 at 9:17
  • \$\begingroup\$ I still don't understand what you're trying to do. Do you want soldermask under the part or not? What does the datasheet say about soldermask under the component? \$\endgroup\$ – DerStrom8 Dec 21 '18 at 14:52
  • \$\begingroup\$ I want Solder Mask in that area. But in Layout, I can have tented via in that area. To prevent that, I want DRC warns me if there are any tented via in that area. So, I was trying to have keepout in solder mask layer in the footprint. Will it work? I understand that I should have keepout in the copper layer. I am just wondering if it is also possible to achieve keepout (like i discussed above) in solder mask layer. \$\endgroup\$ – abhiarora Dec 21 '18 at 15:13

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