PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/output of the PLL. When we choose "non-dedicated" pins, the fitter shall use routing resource to route the pin to the PLL.
I can see that Quartus generates a warning if we do not use dedicated clock pin for input or output. The message usually states that there will be worse jitter performance. It is not clear if this is an actual problem.
In this case, there is a DDR3 memory controller being fed by the clock signal. How do I know if I can get away with using a non-dedicated clock pin for clock used by the memory controller's internal PLL?