# How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/output of the PLL. When we choose "non-dedicated" pins, the fitter shall use routing resource to route the pin to the PLL.

I can see that Quartus generates a warning if we do not use dedicated clock pin for input or output. The message usually states that there will be worse jitter performance. It is not clear if this is an actual problem.

In this case, there is a DDR3 memory controller being fed by the clock signal. How do I know if I can get away with using a non-dedicated clock pin for clock used by the memory controller's internal PLL?

• You start by defining the jitter sources in your system and your timing requirements - setup, hold time, etc. Going against the tool vendor recommendation for a clock source for DDR3 sounds like an exercise in frustration and pain. – Kevin Kruse Dec 18 '18 at 19:50
• I would say, just always use the dedicated pins. What does it cost you to do that? If you don't use those pins for your clock input, you can't (in the parts I'm familiar with) use them for general I/O. – The Photon Dec 18 '18 at 21:30

Suppose the router runs that reference clock input alongside some 2.5 volt FPGA signals that transition in 50 picoSeconds, and the parallel-distance is 1mm and the separation is 1micron. Assume the dielectric constant Er is 5.

Let the reference clock be 10MHz with 1nanosecond edges, and also 2.5 volts swing.

How much jitter will be created? Or another way of thinking, at the zero-crossing of the 10MHz input, how much timing upset will occur. Assume the input clock line has a total capacitance of 10pf.

We simply compute the coupling capacitance between the 2.5v 50 picosecond logic signals and the 10MHz clock with its 10pF, modeling the two series capacitors as a voltage divider.

First: what is the capacitance? Use the parallel-plate model, assume the plates are 1mm by 1micron, and the plate spacing is also 1micron. C = Eo * Er * Area/Distance. We chose to ignore any fringing.

C = 9 e-12pF/meter * 5Er * (1millimeter * 1u)/1u

C = 45 * 1e-12 * 1e-3 = 45 femtoFarad = 0.045 pF

The voltage division ratio is 0.045 pf / 10pF, or 1/222.

The upset voltage at the zero crossing is 2.5v/222 ~~ 10 milliVolts.

Using Tjitter = Vnoise / SlewRate, we have

Tj = 0.01volts / 2.5v per 1nS = 1nS * 0.01v/2.5 = 1nS * 1/250

Tj = 4 picoSeconds

Is 4picoSeconds of deterministic Jitter a problem?

• That's an interesting set of assumptions that you've made to be able to pick a number. Is this based on published information, or is it more of a guess on internal operation? – W5VO Dec 19 '18 at 3:53
• I've used Tj = Vnoise / SlewRate over a wide range of circuits and frequencies, which of course requires straddling circuits, systems, and RF issues, to predict phase noise to about 3dB for a number of situations. Once the tiny spreadsheet I cobbled up indicated we were lucky to have met phasenoise spec (but we did, to everyone's surprise except myself, having spent months thinking thru energy issues behind phasenoise.) The next layer of the onion was the ECL-CMOS converter between LO and the fracN. And yes, there is no published information I used here; just decades of silicon skills. – analogsystemsrf Dec 19 '18 at 4:17
• I think you're assuming a lot about the internal structure of the FPGA, and I'd be willing to bet many of those assumptions are incorrect. While the aggressor-induced jitter calculation looks correct, it's also not clear if that is the dominant source of jitter or how that compares to using the proper clock pin. From those uncertainties, the authority of your "is 4ps of jitter a problem?" seems out of place. – W5VO Dec 19 '18 at 11:49
• yet all the assumptions are laid out, the math is worked out, and the reader now knows how to fish – analogsystemsrf Dec 20 '18 at 3:48
• See comment on fastpath. Dedicated clock pins are best, but other can be used, sometimes. I worked on a DDR controller where the chip designer had put strigent rules on the core clock (because of DDR3 and 10G Ethernet) only to then bond it out on a single ended clock signal way towards the centre of the huge BGA package. It was impossible to get a low jitter 166MHz clock all that way (they relaised their mistake when I showed them the dBc plots). However luckily the DDR3 still worked flawlessly due to it's self calibration. The eye diagrams exceeded the spec dispite the poor clock. – Jason Morgan Dec 20 '18 at 10:11