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VHDL FPGA UART receiver which receives 10 bits via Bluetooth interface. With 8 7-segment displays.

Function Diagram of the UART Receiver

Now my problem is the following

In the requirements it is stated that I have to write the solution in blocks interface which pairs external signal with clock
baud-tick generator
uart state machine
serial to parallel register
7 segment display state machine

I almost got through the task and am hangin on the state machines and their flipflops, see code below. Yes I did research and found different answers to the problem It states that I cannot have if statements in the signals case, but why is it once accepted by my compiler and once not (Cyclone FPGA, Quartus Prime Software)

I get the following error:

Error (10500): VHDL syntax error at uart_state_machine..vhd(53) near text "=";  expecting "(", or "'", or "."

and it looks like it is in my if statement:

if (parallel_in(9) = '1') and (parallel_in(0) = '0') then 

here is the code block

when check_rx =>
            if (parallel_in(9) = '1') and (parallel_in(0) = '0') then 
            data_valid_o = '1';
            next_uart_state <= idle;
            else data_valid_o = '0';
            next_uart_state <= idle;
            end if;
            end case;   

here is the full code:

UART STATE MACHINE

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;

entity UART_STATE_MACHINE is

  port (
    CLOCK_50                :   in      std_logic;
    reset_n                 :   in      std_logic;
   baud_tick_i          :   in      std_logic;
   fall_edge            :   in      std_logic;
    parallel_in         :   in  std_logic_vector(9 downto 0);
    start_bit_o         :   out     std_logic;
    data_valid_o        :   out     std_logic;
   shift_enable         :   out     std_logic
    );
end UART_STATE_MACHINE;

architecture rtl of UART_STATE_MACHINE is
        signal uart_type : uart_state;
        signal uart_type : next_uart_state;
        signal bit_count : integer range 0 to 10 := 10;  -- 10 Bits Total + check_rx
        type uart_type is (idle, prepare_rx, wait_rx_byte, check_rx);


begin


  -- Purpose: Control uart state machine
 ansteuerlogik : process(all)
 begin

 case uart_state is
    when idle =>
            if (fall_edge = '1') then 
            next_uart_state <= prepare_rx;
            else next_uart_state <= uart_state;
            end if;
    when prepare_rx => next_uart_state <= wait_rx_byte;
    when wait_rx_byte =>
            if (bit_count ='1') and (baud_tick = '1') then
            next_uart_state <= check_rx;
            else next_uart_state <= uart_state;
            end if;
    when check_rx =>
            if (parallel_in(9) = '1') and (parallel_in(0) = '0') then 
            data_valid_o = '1';
            next_uart_state <= idle;
            else data_valid_o = '0';
            next_uart_state <= idle;
            end if;
            end case;   
end process ansteuerlogik;

-- FF
ff : process(all)
begin
if rising_edge(CLOCK_50) then
 uart_state <= next_uart_state;
 else
 uart_state <= uart_state;
 next_uart_state <= next_uart_state;
 end if;
 end process ff;

bit_counter : process(all)
begin
---- bit_counter
---with integrated shift_enable 
if (baud_tick_i = '1') and (uart_state = prepare_rx) then
    count = '10';
    shift_enable_o = '1';
    elsif (baud_tick_i = '1') then
    shift_enable_o = '1';
    next_count = count-1;
    else shift_enable_o ='0';
    end if;
end process bit_counter;

end rtl;

BAUD TICK COUNTER

    -- Library & Use Statements
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Entity Declaration 
-------------------------------------------
entity baud_tick_counter is
  generic (width : positive := 10);
  port(clk, reset_n, start_bit : in  std_logic;
       baud_tick_o      : out std_logic
       );
end baud_tick_counter;

-- Architecture Declaration
-------------------------------------------
architecture rtl of baud_tick_counter is
-- Signals & Constants Declaration?
-------------------------------------------
  signal count, next_count : unsigned(width-1 downto 0);
CONSTANT clock_freq : natural := 50_000_000; -- Clock/Hz
CONSTANT baud_rate : natural := 115_200; -- Baude Rate/Hz
CONSTANT count_width : natural := 10; -- FreqClock/FreqBaudRate=50000000/115200 = 434 so need 10bits
CONSTANT one_period : unsigned(count_width - 1 downto 0):= to_unsigned(clock_freq / baud_rate ,count_width);
CONSTANT half_period : unsigned(count_width - 1 downto 0):= to_unsigned(clock_freq/ baud_rate /2, count_width);
-- Begin Architecture
-------------------------------------------
begin

  --------------------------------------------------
  -- PROCESS FOR COMBINATORIAL LOGIC
  --------------------------------------------------
  comb_logic : process(count)
  begin
    if start_bit='1' then
        next_count <= half_period;
    elsif count = 0 then 
    next_count <= one_period;
    else
   next_count <= count - 1;
    end if;
  end process comb_logic;

  --------------------------------------------------
  -- PROCESS FOR REGISTERS
  --------------------------------------------------
  flip_flops : process(clk, reset_n)
  begin
    if reset_n = '1' then
      count <= to_unsigned(0, width);
    elsif rising_edge(clk) then
      count <= next_count;
    end if;
  end process flip_flops;

  --------------------------------------------------
  -- CONCURRENT ASSIGNMENTS
  --------------------------------------------------
  -- take MSB and convert for output data-type
  baud_tick_o <= std_logic(count(width-1));

-- End Architecture 
------------------------------------------- 
end rtl;

DISPLAY OUT

    library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;

entity DISPLAY_OUT_STATE_MACHINE is

port (
    CLOCK_50                :   in      std_logic;
    reset_n             :   in      std_logic;
    parallel_in         :   in  std_logic_vector(9 downto 0);
    data_valid_in       :   in  std_logic;
    reg_out_l_0 :   out     std_logic_vector(3 downto 0);
    reg_out_u_0 :   out     std_logic_vector(3 downto 0);
    reg_out_l_1 :   out     std_logic_vector(3 downto 0);
    reg_out_u_1 :   out     std_logic_vector(3 downto 0);
    reg_out_l_2 :   out     std_logic_vector(3 downto 0);
    reg_out_u_2 :   out     std_logic_vector(3 downto 0);
    reg_out_l_3 :   out     std_logic_vector(3 downto 0);
    reg_out_u_3 :   out     std_logic_vector(3 downto 0);
    reg_out_l_4 :   out     std_logic_vector(3 downto 0);
    reg_out_u_4 :   out     std_logic_vector(3 downto 0)
);
end DISPLAY_OUT_STATE_MACHINE;

architecture rtl of DISPLAY_OUT_STATE_MACHINE is

--- signals
    type display_type is (display_state1, display_state2, display_state3, display_state4);

    signal display_state : display_type;
    signal next_display_state : display_type;

    signal next_reg_out_l_0 :   std_logic_vector(3 downto 0);
    signal next_reg_out_u_0 :   std_logic_vector(3 downto 0);
    signal next_reg_out_l_1 :   std_logic_vector(3 downto 0);
    signal next_reg_out_u_1 :   std_logic_vector(3 downto 0);
    signal next_reg_out_l_2 :   std_logic_vector(3 downto 0);
    signal next_reg_out_u_2 :   std_logic_vector(3 downto 0);
    signal next_reg_out_l_3 :   std_logic_vector(3 downto 0);
    signal next_reg_out_u_3 :   std_logic_vector(3 downto 0);


begin


-- Purpose: Control display state machine
logik : process (all)
begin
--reset
    if (reset_n = '1') then
        next_display_state <= display_state1;
        display_state <= display_state1;
    else
case display_state is
    when display_state1 =>
            if (data_valid_in = '1') then
            next_display_state <= display_state2;
            else 
            next_display_state <= display_state1;
            end if;
    when display_state2 =>
            if (data_valid_in = '1') then
            next_display_state <= display_state3;
            else 
            next_display_state <= display_state2;
            end if; 
    when display_state3 =>
            if (data_valid_in = '1') then
            next_display_state <= display_state4;
            else 
            next_display_state <= display_state3;
            end if; 
    when display_state4 =>
            if (data_valid_in = '1') then
            next_display_state <= display_state1;
            else 
            next_display_state <= display_state4;
            end if; 
            end case;
    end if;     
end process logik;


-- flipflop

flipflops2 : process(all)
 begin
  --reset
    if (reset_n ='1') then

    reg_out_l_0  <= reg_out_l_0 ;
    reg_out_u_0  <= reg_out_u_0 ;
    reg_out_l_1  <= reg_out_l_1 ;
    reg_out_u_1  <= reg_out_u_1 ;
    reg_out_l_2  <= reg_out_l_2 ;
    reg_out_u_2  <= reg_out_u_2 ;
    reg_out_l_3  <= reg_out_l_3 ;
    reg_out_u_3  <= reg_out_u_3 ;

    elsif rising_edge(CLOCK_50) then
    reg_out_l_0  <= next_reg_out_l_0 ;
    reg_out_u_0  <= next_reg_out_u_0 ;
    reg_out_l_1  <= next_reg_out_l_1 ;
    reg_out_u_1  <= next_reg_out_u_1 ;
    reg_out_l_2  <= next_reg_out_l_2 ;
    reg_out_u_2  <= next_reg_out_u_2 ;
    reg_out_l_3  <= next_reg_out_l_3 ;
    reg_out_u_3  <= next_reg_out_u_3 ;
    else
    reg_out_l_0  <= reg_out_l_0 ;
    reg_out_u_0  <= reg_out_u_0 ;
    reg_out_l_1  <= reg_out_l_1 ;
    reg_out_u_1  <= reg_out_u_1 ;
    reg_out_l_2  <= reg_out_l_2 ;
    reg_out_u_2  <= reg_out_u_2 ;
    reg_out_l_3  <= reg_out_l_3 ;
    reg_out_u_3  <= reg_out_u_3 ;
    end if;

end process flipflops2;




--- zuweisungsblock
    output : process(all)
 begin
 -- default
 --next_ ?
    next_reg_out_l_0 <= reg_out_l_0(3 downto 0);
    next_reg_out_u_0 <= reg_out_l_0(3 downto 0);
    next_reg_out_l_1 <= reg_out_l_0(3 downto 0);
    next_reg_out_u_1 <= reg_out_l_0(3 downto 0);
   next_reg_out_l_2 <= reg_out_l_0(3 downto 0);
    next_reg_out_u_2 <= reg_out_l_0(3 downto 0);
    next_reg_out_l_3 <= reg_out_l_0(3 downto 0);
    next_reg_out_u_3 <= reg_out_l_0(3 downto 0);

  case display_state is
    when display_state1  =>
    next_reg_out_l_0(3 downto 0) <= parallel_in(4 downto 1);
    next_reg_out_u_0(3 downto 0) <= parallel_in(8 downto 5);
    when display_state2 =>
    next_reg_out_l_1(3 downto 0) <= parallel_in(4 downto 1);
    next_reg_out_u_1(3 downto 0) <= parallel_in(8 downto 5);
    when display_state3 =>  
    next_reg_out_l_2(3 downto 0) <= parallel_in(4 downto 1);
    next_reg_out_u_2(3 downto 0) <= parallel_in(8 downto 5);
    when display_state4 =>
    next_reg_out_l_3(3 downto 0) <= parallel_in(4 downto 1);
    next_reg_out_u_3(3 downto 0) <= parallel_in(8 downto 5);
    end case;

end process output;

end rtl;

SERIAL TO PARALLEL REGISTER

-- Libraries
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------
-- Entity Declaration 
-------------------------------------------

entity shiftreg_s2p is

  port(
    clk     :   in      std_logic;
    set_n   :   in      std_logic;
    load_i  :   in      std_logic;
    ser_i   :   in      std_logic;
    par_o   :   out     std_logic_vector(3 downto 0)
    );

end shiftreg_s2p;


--------------------------------------------------
-- Architecture
--------------------------------------------------
architecture rtl of shiftreg_s2p is

  signal shiftreg1      : std_logic_vector(9 downto 0);
  signal next_shiftreg1 : std_logic_vector(9 downto 0);

begin
--------------------------------------------------
  -- PROCESS FOR LOGIC
  --------------------------------------------------
  logik1 : process(all)

  begin

    if load_i = '1' then
      next_shiftreg1 <= ser_i & shiftreg1(9 downto 1) ;
        else 
         next_shiftreg1 <= '1' & shiftreg1(9 downto 1);
    end if;

  end process logik1;
--------------------------------------------------
-- PROCESS FOR REGISTERS
--------------------------------------------------

  flip_flops1 : process(all)

  begin

    if set_n = '0' then
      shiftreg1 <= (others => '1');

    elsif rising_edge (clk) then
      shiftreg1 <= next_shiftreg1;

    end if;
  end process flip_flops1; 
--------------------------------------------------
-- CONCURRENT ASSIGNMENTS
--------------------------------------------------
  par_o <= shiftreg1;

-- End Architecture 
------------------------------------------- 
end architecture rtl;

INPUT ALIGNMENT

-- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;

-- Entity Declaration 
ENTITY infrastructure IS
  PORT(     serdata_in      : IN        std_logic;
            reset_n             : IN        std_logic;
            clock               : IN        std_logic;
            serdata_out    : OUT    std_logic
        );
END infrastructure;


-- Architecture Declaration 
ARCHITECTURE rtl OF infrastructure IS

    -- Signals & Constants Declaration 
    SIGNAL shiftreg, next_shiftreg: std_logic_vector(1 downto 0);


-- Begin Architecture
BEGIN 


     -------------------------------------------
    -- Process for Sync (d-flip-flops)
    -------------------------------------------
    dff : PROCESS(clock, serdata_out, serdata_in)
    BEGIN   
        IF reset_n = '1' THEN
            shiftreg(1) <= '1';
        ELSIF (rising_edge(clock)) THEN
            shiftreg(0) <= serdata_in;
            shiftreg(1) <= shiftreg(0);
        END IF;
    END PROCESS dff;    

     -------------------------------------------
    -- Concurrent Assignments  
    -------------------------------------------

        serdata_out <= shiftreg(1);

END rtl;    

HEX TO 7 SEGMENT DISPLAY

-- Library & Use Statements
LIBRARY ieee;
use ieee.std_logic_1164.all;

-- Entity Declaration 
ENTITY hex2sevseg IS
  PORT(
        hexa_i      : IN   std_logic_vector(3 downto 0);  
        seg_o           : OUT  std_logic_vector(6 downto 0)); -- Sequence is "gfedcba" (MSB is seg_g)
END hex2sevseg ;


-- Architecture Declaration 
ARCHITECTURE rtl OF hex2sevseg IS

    -- Signals & Constants Declaration 
    CONSTANT display_0      : std_logic_vector(6 downto 0):= "0111111";
    CONSTANT display_1      : std_logic_vector(6 downto 0):= "0000110"; 
    CONSTANT display_2      : std_logic_vector(6 downto 0):= "1011011";
    CONSTANT display_3      : std_logic_vector(6 downto 0):= "1001111";
    CONSTANT display_4      : std_logic_vector(6 downto 0):= "1100110";
    CONSTANT display_5      : std_logic_vector(6 downto 0):= "1101101";
    CONSTANT display_6      : std_logic_vector(6 downto 0):= "1111101";
    CONSTANT display_7      : std_logic_vector(6 downto 0):= "0000111";
    CONSTANT display_8      : std_logic_vector(6 downto 0):= "1111111";
    CONSTANT display_9      : std_logic_vector(6 downto 0):= "1101111";
    CONSTANT display_A      : std_logic_vector(6 downto 0):= "1110111";
    CONSTANT display_B      : std_logic_vector(6 downto 0):= "1111100";
    CONSTANT display_C      : std_logic_vector(6 downto 0):= "0111001";
    CONSTANT display_D      : std_logic_vector(6 downto 0):= "1011110";
    CONSTANT display_E      : std_logic_vector(6 downto 0):= "1111001";
    CONSTANT display_F      : std_logic_vector(6 downto 0):= "1110001"; 
    CONSTANT display_blank  : std_logic_vector(6 downto 0):= (others =>'0');


-- Begin Architecture
BEGIN

  -------------------------------------------
  -- Concurrent Assignments  
  -------------------------------------------
  -- Implementation option: concurrent comb logic with with/select/when
  WITH hexa_i  SELECT
    seg_o <=    NOT(display_0) WHEN x"0",
                    NOT(display_1) WHEN x"1",
                    NOT(display_2) WHEN x"2",
                    NOT(display_3) WHEN x"3",
                    NOT(display_4) WHEN x"4",
                    NOT(display_5) WHEN x"5",
                    NOT(display_6) WHEN x"6",
                    NOT(display_7) WHEN x"7",
                    NOT(display_8) WHEN x"8",
                    NOT(display_9) WHEN x"9",
                    NOT(display_A) WHEN x"A",
                    NOT(display_B) WHEN x"B",
                    NOT(display_C) WHEN x"C",
                    NOT(display_D) WHEN x"D",
                    NOT(display_E) WHEN x"E",
                    NOT(display_F) WHEN x"F",
                    NOT(display_blank) WHEN OTHERS; 


END rtl;

at the end it is a simple syntax question:

is this allowed:

when check_rx =>
            if (parallel_in(9) = '1') and (parallel_in(0) = '0') then 
            data_valid_o = '1';
            next_uart_state = idle;
            else data_valid_o = '0';
            next_uart_state = idle;
            end if;

this syntax: if (parallel_in(9) = '1') and (parallel_in(0) = '0') then

to check for the MSB and LSB

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  • \$\begingroup\$ Have you checked if the syntax in the vicinity of the reported syntax error? Specifically: have you checked that you use the same syntax to write statements as you do at other parts of your code? \$\endgroup\$ – DonFusili Dec 20 '18 at 11:31
  • \$\begingroup\$ i think it has to do that I check for the last and first bit parallel_in(9) and parallel_in(0) and I check for both in the same if statement : if (parallel_in(9) = '1') and (parallel_in(0) = '0') then I brought it down from 19 errors to 4 which are all the same type (not considering that there may be systemic errors in the code, like total wrong assignements of flipflops etc so any help would be really appreciated ! \$\endgroup\$ – CircuitBender Dec 20 '18 at 11:36
  • \$\begingroup\$ Let me put it this way: I know you didn't simulate this code, because it's also functionally worthless considering your data valid will never be high. \$\endgroup\$ – DonFusili Dec 20 '18 at 11:40
  • \$\begingroup\$ That is clear ! How can I simulate if I get errors just trying to compile the block diagrams, (if this helps and I should have simulated it, please instruct me how to do so) and for sure data_valid never goes high, because in the if statement where it is decided that data_valid = 1 I get the error I am describing would it be a possibility to write a own process for the whole data valid thing and leave it out in the when case ? just trying to learn and get the hang out of vhdl and admitting that c++ is more my kind of a base \$\endgroup\$ – CircuitBender Dec 20 '18 at 11:45
  • 2
    \$\begingroup\$ I took your UART_STATE_MACHINE code only and run it through Vivado. It is full of errors from top to bottom. I suggest you take one module and slowly start adding code line-by-line and compile in between. For now start with correcting the defining of your uart_state and uart_next_state signals. You have the variable and type the wrong way around! Also define the type before you use it. I don't know if that is needed (I am a Verilog man, not VHDL ) but it is good coding practice. Take it slow and take your time. You get ahead faster that way. \$\endgroup\$ – Oldfart Dec 20 '18 at 12:06
3
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The answer to your actual question is that it isn't the if ... then line that's causing the error; it's the assignment statement on the next line: data_valid_o = '1'; You can't use '=' as an assignment operator in VHDL; it's strictly a relational operator.

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  • \$\begingroup\$ thx so much ! so I will use := ? \$\endgroup\$ – CircuitBender Dec 20 '18 at 13:38
  • 2
    \$\begingroup\$ @CircuitBender You are assigning a signal, not a variable... You shouldn't use :=... You should use <=. \$\endgroup\$ – CapnJJ Dec 20 '18 at 14:19
  • \$\begingroup\$ The fact that the error message was quite clear about the error and that the OP is misunderstanding assignment operators tells me that this might be a little bit to difficult to start with? \$\endgroup\$ – Humpawumpa Dec 20 '18 at 15:19
  • \$\begingroup\$ critisizing OP is not helping OP did admit he is a NOOB whats the problem ? it was a simple question \$\endgroup\$ – CircuitBender Dec 20 '18 at 16:57
  • 1
    \$\begingroup\$ @Humpawumpa "...and that the OP is misunderstanding assignment operators..." VHDL doesn't have assignment operators. Assignment is a basic operation. IEEE Std 1076-2008 5. Types, 5.1 General, paragraph 3. Assignment statements are described in an intermediary syntactical production in BNF (10.5 Signal assignment statement, 10.6 Variable assignment statement, 11.6 Concurrent signal assignment statement) requiring compound delimiters ("<=", ":=", 15.3 Lexical elements, separators, and delimiters). VHDL has no assignment expressions, they're all statements. \$\endgroup\$ – user8352 Dec 21 '18 at 5:02

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