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As far as I understand, in an AC circuit, a capacitor is supposed to charge as the voltage is increasing, and as soon as the voltage starts decreasing, the capacitor starts to discharge (Since it will be the higher voltage source out of all in the circuit by then).

But in a clamper circuit, for instance in the one below: Negative Clamper

In the positive half cycle, the diode should conduct, and the capacitor should charge. But as soon as the input voltage starts decreasing from Vm, shouldn't the capacitor start discharging?

Also, since the diode is forward biased, shouldn't the output be zero during the positive half cycle?

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    \$\begingroup\$ See my updated answer. \$\endgroup\$ – Dan Khan Dec 20 '18 at 16:21
  • \$\begingroup\$ To maybe help your insight: C blocks any DC component, so what you see at the output will not be influenced by any DC component (battery in series with your Vi).So you can imagine such an offset of -Vm. \$\endgroup\$ – Wouter van Ooijen Dec 20 '18 at 16:57
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The simple analysis of this circuit considers the diode internal resistance, Rd, vs the load resistance, R1. This ratio determines the ratio for charge/discharge time constants. The value of C scales both of these ratios to achieve the actual times.

charge T1=C * Rd vs. discharge T2=C * R1

By design, the discharge rate is slow by choosing T2 >> 1/f

Below the diode and load R are chosen to have a ratio of decay to rise time of 10k/10= 1000.

schematic

simulate this circuit – Schematic created using CircuitLab

Other details

But we must also consider the added series resistance in the loop from the Source, Rs and the Capacitor ESR. Generally ultra-low ESR e-caps have an ESR*C=T<10us and ceramic <<100ns but also depends on size and voltage rating which also affects the Self Resonant Freq of the cap, normally not an issue in this circuit.

The diode Rs is the incremental resistance of Vf at some charging current Rs=ΔVf/ΔIf. I know from experience this Rs is usually same or less than it's Power Rating so a 100mW diode would be approx 10 Ω (ballpark) and a 1W diode < 1 Ω. The higher peak currents may drop this to Rs=1/4Pd. This applies to most diodes.

Thus charge time above becomes T1=C*(Rs+ESR+Rd)

But if R1 becomes too large then the cap & diode reverse bias leakage currents must be converted to some equivalent resistance, usually > 100k but again depends on each part datasheet specs, such as Schottky diodes leak more than Silicon yet have a lower Vf.

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  • \$\begingroup\$ I'm not sure if I understand this correctly. I believe it is telling us that the rate of capacitor discharge will be much slower than the rate of charging. Still, that doesn't clarify for me why the waveform doesn't change when the capacitor starts discharging in the positive half of the cycle itself? \$\endgroup\$ – Kishore Ganesh Dec 21 '18 at 9:01
  • \$\begingroup\$ It would, if you choose too low a frequency or too low a value of R1C=T which by design is T >> 1/f \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 21 '18 at 13:00
  • \$\begingroup\$ If you chose the values such that the discharge rate were extremely slow, thus not affecting the positive half cycle of the waveform, then shouldn't it also not affect the negative half cycle too? Am I missing something? \$\endgroup\$ – Kishore Ganesh Dec 22 '18 at 9:27
  • \$\begingroup\$ So there'll be periods when the waveform is actually blank, right? Initially, in this circuit, the waveform will be blank as long as the capacitor is charging. As soon as it reduces from Vm, the waveform assumes the clamped shape. Over time, the capacitor is discharged, and htis happens again. \$\endgroup\$ – Kishore Ganesh Dec 22 '18 at 9:42
  • \$\begingroup\$ The diode clamps the positive input while charging the cap to the peak voltage rapidly then the diode shuts off and the decay is slow as the cap passes the signal out as a negative output ,with very slow R1C decay. This is a positive clamp. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 22 '18 at 16:49
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The capacitor will discharge during the negative-going half-cycle - but slowly, with the time constant determined by the capacitor and resistor values. In this circuit we would normally select R and C values sufficiently large that the capacitor will not discharge significantly in one cycle.

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  • \$\begingroup\$ I'm not talking about the negative half cycle, I'm talking about the decreasing part of the positive half cycle. In the analysis I have studied about capacitors in AC circuits, they oppose changes in voltage. So shouldn't the capacitor start discharging in the positive half cycle itself. \$\endgroup\$ – Kishore Ganesh Dec 20 '18 at 16:07
  • \$\begingroup\$ Sorry - I should have said "while the voltage is falling". Still, the time constant should be sufficiently long that the capacitor will not significantly discharge. \$\endgroup\$ – Peter Bennett Dec 20 '18 at 16:10
  • \$\begingroup\$ Ah, so it does discharge a bit. I was confused because no book seemed to mention it discharging in the positive cycle itself. But then shouldn't that cause changes in the output waveform, since it is discharging through R? \$\endgroup\$ – Kishore Ganesh Dec 20 '18 at 16:12
  • \$\begingroup\$ You choose R and C values so that any changes caused by the discharge are insignificant for your application. \$\endgroup\$ – Peter Bennett Dec 20 '18 at 16:15
  • \$\begingroup\$ I'm still not able to understand it. Even if we chose a very large R, thus causing a very slow discharge, there should still be a voltage drop across it, due to which we'll be getting a different waveform from what is predicted, right? Also, would you agree that in the positive half cycle, the output should be zero, since the circuit will be short-circuited? \$\endgroup\$ – Kishore Ganesh Dec 20 '18 at 16:18
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Update :

During the negative half cycle of the input AC signal, the diode is reverse biased and hence the signal appears at the output. In reverse biased condition, the diode does not allow electric current through it.

So the input current directly flows towards the output. When the negative half cycle begins, the diode is in the non - conducting state and the charge stored in the capacitor is discharged (released).

Therefore, the voltage appeared at the output is equal to the sum of the voltage stored in the capacitor (-Vm) and the input voltage (-Vm) {I.e. Vo = -Vm - Vm = -2Vm} Which have the same polarity with each other. As a result, the signal is shifted downwards as shown in the output.

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  • \$\begingroup\$ I believe you're talking about the negative half cycle, when the capacitor actually starts discharging and we have 2vm as output. But I'm asking for the positive half cycle itself, where the capacitor should start discharging when the input voltage drops from Vm to zero. Because capacitors are supposed to oppose changes in voltage? \$\endgroup\$ – Kishore Ganesh Dec 20 '18 at 16:10
  • \$\begingroup\$ But why should it hold the charge? Because at the instant the input voltage starts decreasing, the capacitor should be the bigger voltage source in the circuit. Thus it should result in current flowing through the opposite direction, and the capacitor discharging through R. \$\endgroup\$ – Kishore Ganesh Dec 20 '18 at 16:23
  • \$\begingroup\$ I have done another update please check it that should have answered your question. \$\endgroup\$ – Dan Khan Dec 20 '18 at 16:34
  • \$\begingroup\$ I'm following on the negative half cycle part. But the problem I have is with the positive half cycle, in which the capacitor should start discharging as soon as the wave goes from Vm to zero, since it opposes changes in voltage. \$\endgroup\$ – Kishore Ganesh Dec 21 '18 at 9:03
  • \$\begingroup\$ It does discharge look at the output. However it’s phase is shifted downwards. It’s the same but the wave in the output has just moved downwards. \$\endgroup\$ – Dan Khan Dec 21 '18 at 9:48

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