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Part of the Dual Slope ADC consists of an integrator which integrates the input voltage according to Vin/-Vref . I am using TL071 connected as an inverting integrator.

Quick summary of operation: The output of the integrator charges negatively up to a certain count value when Vin is connected. When the count value is reached, the controller switches to -Vref. This causes the integrator to discharge and hence increasing output voltage (note due to inverting output).

NOW... Instead of the integrator to continue to integrate towards a positive output voltage while -Vref is connected, I want it to stop at zero voltage so that when Vin is connected as input, the integrator will start integrating negatively instantly.

Is this possible by connecting the op-amp supply terminals +Vcc to ground while -Vcc to -ve supply? I tried this but observed clipping in the negative rail too, is it a bad approach? Any other possible solutions?

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  • \$\begingroup\$ Could you add a schematic to your question? \$\endgroup\$
    – Kevin Brant
    Dec 21, 2018 at 22:09
  • \$\begingroup\$ Connect the input voltage to ground, and connect a resistor across the integrating capacitor. This is easy to do with analog switches. \$\endgroup\$
    – TimWescott
    Dec 21, 2018 at 22:16
  • \$\begingroup\$ Ah yes, was thinking of that so like a switch with enable function so that when integrator reaches zero, MCU sends a signal to the switch to connect the input to ground if I'm on the right track? Or maybe would it be possible to add a mosfet with enable across the capacitor to hold the integrator in reset mode till MCU is ready for another conversion? \$\endgroup\$
    – Simon Sultana
    Dec 21, 2018 at 22:41

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@Tim's suggestion is a good one. An analog switch across the integrating capacitor with the inputs grounded. Note that it's usually better to use the same resistor for integrate and de-integrate, though if your switch has a lot of charge injection it might cause issues. Ideally the value of the resistor, the capacitor value and the absolute clock frequency will cancel out.

You might find the front end of a typical ca. 1990 DVM chip of interest:

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In the auto-zero (AZ) phase, the comparator output is fed back to the integrator input. The differential inputs are shorted and grounded. This causes oscillation at the comparator output but it results in charging Caz to compensate for the offset voltage of the integrator and input buffer, meaning a lot better precision for the relatively poor performance of those op-amps. Typically it will auto-zero within tens of uV.

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By including a few extra switches they allow a fully differential floating reference voltage via a "flying capacitor" Cref.

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