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The FSM shown by both the table and state diagram perform Division by 5 on a binary input A. The individual states represent the remainders and the transition outputs are meant to be loaded into external shift register.

The FSM below takes an input stream of bits that are separated into chunks by a control signal c. When c goes from 0 to 1 it indicates MSBs and when it goes from 1 to 0 indicates LSBs, the FSM must remember this active high state where c=1 until control signal is set to c=0. How can I correctly implement a sixth state to my FSM that performs this control mechanism. I know that c needs to be an input to my fsm in addition to a0 and a1 bits(see problem statement below)

Edit: I added a few redundant statements here, but really all the information is already provided below. Please add helpful comments indicating what info is missing that would help you understand this question more. The problem statement!]1

NSTT for my 2-bit divider fsm

State diagram for a 1-bit x/5 divider fsm (same issue with lack of control state)

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    \$\begingroup\$ Why don't you write some more of your own words (not those of some book or lesson) about how you are thinking about this problem? You have a "title," followed by one single sentence. You did write a comment line. I'll grant that. But seriously? Perhaps you could write a little more from your own perspective? \$\endgroup\$ – jonk Dec 25 '18 at 2:51
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    \$\begingroup\$ I do understand and I've worked out a completed solution. Feel free to search my other answers. You'll see some basic skills in this area, if you do. It's my own opinion you hadn't written enough. That's all. Others are free, of course, to disagree. \$\endgroup\$ – jonk Dec 26 '18 at 4:09
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    \$\begingroup\$ The following is intended to be helpful, not critical. When people come with questions which are largely textbook based the suspicion is, and the reality often is, that this is an assignment/homework/ ... and that we are being asked to do a student's work. The issue is not usually a matter of understanding but of wanting people to learn correctly and not fail because others do their work for them. This is not (usually) a self righteous desire to kick out the lazy ones but a genuine desire (usually) to help appropriately. ... \$\endgroup\$ – Russell McMahon Dec 26 '18 at 11:39
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    \$\begingroup\$ In such cases people are usually willing to engage with people who show appropriate effort and interaction. | In your case it seems likely that you largely 'know your stuff' and have come with a legitimate query - but Jonk is (as far as I can tell) wanting you to engage. He is not (probably) asking for data per se but for your understanding to be shown and where your limitations are that need addressing. | In some cases what looks like course work is actually someone commendably seeking to learn on their won and/but such cases also need to be presented so others can understand. \$\endgroup\$ – Russell McMahon Dec 26 '18 at 11:42
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    \$\begingroup\$ ie "We're here to help" :-) - What is your need in context? [FWIW - I recall last looking at specific material covering your question about 40+ years ago. I could probably dig out enough to awaken the long damped memories and use Googlabet to rapidly come up to speed. But Jonk is liable to help an order of magnitude faster :-) ]. \$\endgroup\$ – Russell McMahon Dec 26 '18 at 11:44
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How's this?

This 10 state Mealy FSM uses an additional 5 states for remembering where the C_in = 0 and therefore indicating the input of the last two LSBs of the binary dividend. The input bits a_0 and a_1 are X(don't cares) for when c=0. If from a state where c=0, a next state input c=1, then the state transitions to the reset state with an output of zeroes.

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