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I've been trying to get this question done for a couple of days now and no matter how much I try I've been unable to get it done. Your help in this question is greatly appreciated.enter image description here

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    \$\begingroup\$ You must first show us your best attempt. What does your book say about this? \$\endgroup\$ – G36 Dec 24 '18 at 10:53
  • \$\begingroup\$ Thank you for your reply! I've read a lot about JFET biasing from a book called "Electronic Devices and Circuit Theory". It gives many great examples of how to tackle problems of Voltage Divider biased JFETs. However, it doesn't talk much about designing JFET circuits. The one condition I thought might help me but I'm not very sure of is the condition that says that when ID = 0, VG = VGS. However, even with that I'm still very unsure whether this is correct or not. \$\endgroup\$ – James Ronald Dec 24 '18 at 11:06
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    \$\begingroup\$ Can you design a circuit for Idq = 3mA without worrying about Idss and Vgs(off) variations? \$\endgroup\$ – G36 Dec 24 '18 at 11:14
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    \$\begingroup\$ Look at the example here electronics.stackexchange.com/questions/391791/… \$\endgroup\$ – G36 Dec 24 '18 at 11:16

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