High speed signals require special care in PCB layout to prevent high speed effects like ringing and overshoot. This obviously applies to clock signals as well.

Provided that one has a high voltage clock (e.g 3.3V) and wants to connect it to a low voltage input of an FPGA e.g 1.2V, one could use a voltage divider.

  1. Are there any disadvantages in general in dividing clock signal like this e.g increased noise or jitter?
  2. How should the voltage be reduced in a high speed signal e.g clock that is 100s of MHz?
  • \$\begingroup\$ You should use a level translator IC for 3.3 V to 1.2 V. Of course this IC should be rated for a high speed clock signal. \$\endgroup\$
    – Uwe
    Dec 24, 2018 at 13:44

2 Answers 2


The rules are that you must take into account impedance requirements and consider the effective RC network created by a voltage divider when considering track capacitance. See this excellent application note.

Dividers even at 33MHz are not going to work well, if at all, and I say that from personal experience where I advised against it but it was done anyway with the attendant pain of rework when the clock was not good enough any more. Remember that it is the clock edge you need to preserve.

It might be possible if you use a buffer immediately after a voltage divider, but you are likely to have duty cycle and phase issues relative to the original clock signal.

Track capacitance for a 100 micron track spaced 100 micron from the ground plane is about 1pF per 25mm of track. Even with short tracks and using a 50 ohm divider there is a low pass filter of 530MHz for a 6 inch distribution track and the attendant extra drive requirement on the source. Note that a low pass filter adds deterministic jitter to a high speed signal. PCB tracks (including differential pairs) are low pass filters as well so adding another filter simply adds more attenuation to the overall clock signal.

I would usually use a clock system where the various levels are generated from individual ICs; there are a number of such offerings.

There are translation products available should that actually be necessary.

For an FPGA, I would normally feed a lower frequency clock and use the (commonly available) internal PLLs to generate any really high frequency clocks.

  • \$\begingroup\$ A low pass filter degrades the dataeye. Is that the same as Jitter increasing? \$\endgroup\$ Dec 24, 2018 at 18:32
  • \$\begingroup\$ @analogsystemsrf: yes, jitter does degrade the eye by increasing ISI. \$\endgroup\$ Dec 25, 2018 at 7:30

There is no magic; clocks are the same signals as any other. If you want a clean signal in 30+ MHz area, you need to take into account:

  1. Traces behave as transmission lines. Threat them as such; typical thin trace has about 65-80 ohms of characteristic impedance, and for more accuracy check your particular PCB layout.
  2. Output and input pins of ICs have capacitance, 2-10 pF typically;
  3. An output driver has a finite impedance. Assume 25 ohms for starters, and check with the manufacturer. If Voh and Vol are only given, use this recipe;
  4. Match the impedance on the input and output of the transmission line;
  5. Use a simulator (or common sense) to do #4.

Here is a network that I made using LTSpice, using the above assumptions (3.3 V source, 1.2 V destination):

Enter image description here

It is for a 50-MHz clock and ~ 6" trace (~ 1 ns delay). In the worst case you will need three resistors. That's it.


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