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I recently read something about the latch-up effect in CMOS-Structures but I don't understand why are MOSFETs affected by this effect. I understand that high currents through the source-drain path cause this effect because there are npn-pnp structures in the substrate which form transistors.

But I often read that "high" voltages (VDD + 0.7 V) on the input also causes latch-ups which is a problem if the device of the input is powered of. A logical one (active) would cause a latch up because 3.3V > 0 V + 0.7 V.

Why does this cause a latch-up? I thought latch-ups are caused by high currents. But the gates are isolated which does not permit any flow through the source-drain path, especially if the device is powered off. I see only a problem through the powering on phase where the operational voltage clamps up.

So my question is: Why do "high voltages" on the input cause latch-ups too and why is the condition VDD+0.7 V (VDD + Diode drop)? How can I protect CMOS inputs against latch-ups through signals which occur even if the device is powered off?

I would by very happy about answers :)

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    \$\begingroup\$ To understand latch-up you have to see where the NPN/PNP structures are in a side-view of a CMOS process. Then consider what could make the parasitic NPN/PNP go into forward mode. Without understanding that it is impossible to understand when latch-up can occur and what can be done about it. Have you read: ti.com/lit/wp/scaa124/scaa124.pdf ? Or watched: youtube.com/watch?v=gIleH0fH6nM \$\endgroup\$ – Bimpelrekkie Dec 24 '18 at 13:08
  • \$\begingroup\$ I know the parasitic transistors but I wasn't aware of the ESD protection diodes as TimWescott pointed out. \$\endgroup\$ – Sebi2020 Dec 25 '18 at 19:47
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Why do input voltages more than one diode drop above VDD or below VSS cause latch-up?

Because nearly all CMOS chips have ESD protection diodes, and those diodes are part of the latch-up process.

See figure one of this app note from TI. It shows the parasitic thyristor in a typical CMOS gate, including the ESD protection diodes.

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Summary: view the well/tub/substrate as the BASE of the parasitic bipolar.

Now decide which of the various other structures can inject charge, and when that charge will be gathered up.

If there is 0.5 or 0.6 or 0.7 volts drop between the "gather up" structure and that usually rather large BASE, you are at risk.

One way to prevent the latchup is to CAPTURE the charges into low resistance nodes (often Wellties or SubTies) that are so widely distributed that the 0.5/0.6/0.7 volt drop cannot occur.

Thus a dense arrangement, of intermixed WellTies and Source Contacts, may be the cure.

THIS TOPOLOGY FAILED.

schematic

simulate this circuit – Schematic created using CircuitLab

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Others have given examples of latchups mechanisms.
Many modern ICs incorporate structures to reduce latchup affects. For example, see section 2.2 page 5 in the TI / Sylvania Latch-Up, ESD, and Other Phenomena application note that Bimplerekkie cited in his comment.

As well as the more intuitive specific mechanisms described in that paper, there is Murphy. If you apply voltage to a device pin at a level sufficient to cause current flow via routes other than intended by the circuit designer then clearly "it may go somewhere and it may do something".
'Somewhere' and 'something' may not be well defined, but it's not hard to think of numerous - 'it MIGHT just do this' scenarios. Among these is the injection of current into nodes that are isolated in normal operation and which may have no formal discharge path. Such isolated nodes can be charged to various voltages and are then available for Murphy to utilise to best effect.
The formation of spurious "floating gate" FETs or activation or deactivation of formal FETs within a device can occur - and sometimes does.

Effects that I have seen include:

  • Injection of low level currents during power down due to some pin voltages decaying faster than others causing IC "freezing" - power must be removed for 5+ minutes before they would restart OR all pins needed to be "hard grounded" - at a minimum substantially below 0.6V. This was not classic latchup which results in a high current path between supplies and possibly in IC destruction. The IC was "latched up" inasmuch as it was wholly inoperable, but non destructively. For me this occurred in a commercial design utilising the ISD2500 speech storage IC. It was prevalent enough that the manufacturer were interested in my workaround.
    My "fix" was to provide a resetting circuit which caused hard clamping of the 5V supply rail as soon as it had fallen to say 5V. This overcame the problem by never allowing the cause to occur. .

  • ADC (Analog to Digital) converters in microcontrollers giving inaccurate or totally loony results when mere microamps were injected into digital pins physically near the ADC pins on the package. This has been reported by a number of people.
    Fix: Follow the spec sheet.

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  • \$\begingroup\$ But how would you protect the input pins of a serial interface against latch-ups, for example? It cannot be said, whether a user does not already try to send data before the receiver is powered on. Thats why some sort of latch-up protection seems to be necesarry to me. \$\endgroup\$ – Sebi2020 Dec 25 '18 at 19:56
  • \$\begingroup\$ @Sebi2020 your 2nd point 1st. Yes, 'protection' is necessary in any circuit where it's absence means that the system violates formal operating mode specifications. Many systems violate specifications often and have no problems. Murphy says that this still may happen if they are half a world away and filling an important function :-). | ... \$\endgroup\$ – Russell McMahon Dec 26 '18 at 11:03
  • \$\begingroup\$ @Sebi2020 ... 1st question: If currents can be reduced to around the microamp level they are very unlikely to cause major issues. But still might. A serial input say can be protected by adding circuitry that always constrains V_IC_input to at or within the supply rails. This is seldom hard to achieve technically, just more annoying than people like to accommodate. eg adding a series input resistor to a node A, two reversed Schottky diodes to supply and ground , another series resistor from node A to input pin and another pair of Schottky's at the pin will provide good results, usually. \$\endgroup\$ – Russell McMahon Dec 26 '18 at 11:05

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