I am designing a high voltage board, 10,000 VDC. I wish to use a suitably rated capacitor such as the
DHR4E4A102K2BB. When I have been studying the
IEC 61010 standards the conductor clearance should be in the order of 0.00305 mm/volt, therefore you would think that for a 10kV rated capacitor the lead spacing should be at least 30.5mm.
However, when looking at many datasheets they are around 9.5mm +/-2mm.
In my application one lead needs to be at 10kV and the other at 0V, so I would expect arcing/flash over to occur.
What am I missing?
EDIT TO SHOW PCB
EDIT TO SHOW SCHEMATIC
Schematic added to show that is I added DC grading resistors in parallel to the capacitor then it would create a potential divider network and my outputs would be less than 10kV. Hence the discussion about
headroom. I have 10kV coming in and I need 10kV (or there abouts) going out.