I'm working through implementation of the SAP-2 CPU from Digital Computer Electronics, 3rd Edition.
I'm having difficulty understanding how the arithmetic & logical instructions can be implemented in only 4 T-states. Let's take the "ADD B" instruction as an example, which adds the contents of register B to the accumulator (register A).
This CPU design uses 3 T-states to fetch/decode, so the third rising edge latches the instruction into the instruction register from RAM.
That leaves me only one cycle to perform the addition.
Unfortunately, this CPU design also has the ALU hard-connected to the accumulator (A) and a temp register (TMP).
So, I can set up my control word so that on the 4th rising edge it will "enable B" to write to the bus, "load TMP" to receive the value of B, and also set the ALU to addition mode. But, I can't get the sum back out of the ALU and into A during that same rising edge. The data bus is already in use with the B->TMP movement, and the result from the ALU won't be ready yet anyway.
I feel like I'd need a 5th cycle where the control word is set up "enable ALU" & "load A" to store the result back into A, and also set "load flags" to latch the zero and overflow flags.
What am I missing? How does the SAP-2 do all this during just the T4 state?