3
\$\begingroup\$

I'm designing a PCB with some noise-sensitive components (FPGA, RF mixer, etc.). For the power systems I've decided to chain switching regulators to LDO regulators so that I get less heat dissipation and better noise performance than either alone. However, I'm unsure as to the optimal location of the LDO regulators. My thought is that they should be placed near the outputs of their corresponding switching regulators so that switching noise is confined to the edge of the board. Or is it better to place them near the loads they drive? The second setup could result in a slightly more accurate voltage across the load since less of the LDO output voltage will drop across the power traces, but since my board isn't too big and I have room to make the power traces wider if need be, I'm not too worried about that. I'm also not too worried about trace inductance because the bypass capacitors should take care of that.

What else am I not considering here? Is there a typical way this is done?

\$\endgroup\$

4 Answers 4

2
\$\begingroup\$

I'm unsure as to the optimal location of the LDO regulators.

LDOs regulate output voltage relative to their own GND pin, and the capacitor which is usually placed right at the output for stability will link the local GND with the output at HF too. So if you have substantial current in your ground plane, GND may not be the same voltage everywhere. Just like voltage drop from trace resistance, this is an argument to place the LDO closer to the load.

It is very important to not screw up the switchers layout also.

Now you have to consider each load both as a potential victim of noise ingress but also as a noise generator. So, for each load consider current and voltage but also noise tolerance at various frequencies, etc. Then, consider the current that is drawn by the load, is it constant, spiky, random, HF, etc?

Each load will be sensitive (to various degrees) to supply ripple and noise, but each load will also generate ripple and noise on its supply.

This also depends on the time scale. For example, if you got USB2 then there is a chip in your design that will draw current spikes at 8kHz each time it processes a packet. Average current draw will be constant but the power rails of this chip will have 8kHz ripple. If you check the analog output of some USB soundcards... you will very often find some garbage at 8kHz, and if you're lucky, the signal may even intermodulate with the 8kHz stuff, like if the DAC reference voltage is a bit too friendly with the power supply of the USB chip.

A crystal oscillator can draw constant average current (the switching spikes are averaged by the local decoupling cap) but it might turn power supply noise into phase noise.

Then you can split it into power domains, and fence these with ferrite beads or use several LDOs. It depends a lot on the noise frequency bands.

For example if you have a 5V switcher supplying both:

  • a microcontroller which doesn't care about supply noise but generates wideband noise
  • and an opamp with excellent LF PSRR but bad HF PSRR, it draws variable current too in order to supply its load

In this case we connect the micro to the switcher output. And, since the opamp will reject LF noise and supply ripple well, it doesn't care if we add an extra ohm in its power supply line. If it draws a variable current of a few tens of mA, then it will wobble its own supply by a few tens mV, if it has 80dB PSRR at that frequency, that's no concern. So this opamp doesn't need a local LDO, however it needs a supply without HF noise on it, which means a ferrite bead in its power supply with a local decoupling cap (make sure these don't resonate).

So try to keep this in mind, group loads on power domains by how well they will work together, then apply LC filters where needed to prevent cross-contamination, then decide how many LDOs you need.

LC filters block high frequency noise, but let LF noise through. Your LC filter will usually be a Pi filter since there will most likely be a cap on both sides of the ferrite bead... which means it prevents HF noise from getting into the load, but it also prevents HF noise generated by the load from contaminating the main supply. The local decoupling caps provide a small loop for HF current and the ferrite adds impedance to make sure HF load current doesn't go where you don't want it to.

LDOs remove low-frequency ripple and noise, but at HF the pass transistor is a capacitor, so HF noise goes through. Parasitic capacitance increases as dropout voltage decreases, so higher efficiency means worse HF PSRR. Also, the LDO draws its current from the supply, so it passes on variable load current to the main supply. This is only at LF though, so less of a problem.

To remove both frequency bands, you can use a LC filter followed by a LDO.

A few cents in LC passives plus a cheap LDO may have higher PSRR than a high-end, "high HF PSRR" LDO. And passives are the only solution to get decent rejection above 10MHz.

A high current filter right at the output of the switcher may not be the ideal solution. Maybe your FPGA draws lots of current on 3V3 VCCIO but it doesn't care about the noise. So you can use a much smaller cheaper low current filter just for the sensitive parts on 3V3, like the clock or whatever. Beads perform better at low DC current, less core saturation.

\$\endgroup\$
0
3
\$\begingroup\$

Just consider the inverse load regulation error of the LDO and add the resistance of your trace and return path. It may be negligible, so it does not matter here.

Typically the series output incremental or "knee resistance" is 1 or 2% of the rated voltage/current which is the same thing as your output Load Regulation error.

e.g. 5V/1A = 5 Ω so 1% of this is 50 mΩ. Your ESR of your output cap needs to be much lower than this (if you need) to get the pulse load error much less than Step load Regulation error.

Your trace inductance and resistance may be computed to compute your pulse load response for ringing or noise. The Zout of the LDO rises with frequency from DC because the loop bandwidth for negative feedback inside the LDO also decreases to unity at the breakpoint. This is useful, because that also reduces the Q of the pulse noise resonance.

Since RF circuits are generally supply noise sensitive, the impedance of the tracks needs to be compared with the impedance of low ESR cap at the equivalent frequency of the pulse load to compute the peak to peak error in DC amplitude. But for a known current pulse duration, track resistance and inductance 10nH/cm typ you can compute these easily. Most likely the location of the LDO is less important than the choice and location of output Cap recommended by the LDO datasheet.

Always start with Design specs for RF Vdc tolerance, ripple, Idc and Iac vs f and do an impedance or at least a step voltage simulator plot to anticipate problems and non-problems that you are trying to fix. LDO's rise in output impedance with frequency.

If these specs are not known, then breadboard a test circuit to find out unwanted susceptibility and interference and required attenuation. Never assume.

\$\endgroup\$
2
\$\begingroup\$

There are some considerations that can be made and all depends on the components and layout you'll use. The switcher-LDO cascade is indeed a usual configuration but care needs to be taken with the switching frequency with respect to the PSRR of the LDO at the switching frequency. Take an old 780x for example with a 1MHz switcher: from the top of my head, in this case the linear regulator (not an LDO) will do little with regard to the ripple of the output.

The high current (or high dV/dt) path of the switcher layout is the most important. If there is a single low impedance track, pour or plane from switcher to LDO, then there is not much to worry about and your layout can be whatever suits you best. Things can get worse with many plane changes, many or long stubs. Avoid those as they could start radiating. And decoupling everywhere: input and output of switcher, input and output of LDO, bulk capacitance between switcher and LDO. Keep these things in mind and you should be safe.

\$\endgroup\$
1
\$\begingroup\$

The ripple(1MHz) and ringing(10MHz to 100MHz) from Switching Supplies will not be attenuated by LDOs. Their task is to attempt to regulate DC output, and perhaps attenuate input ripple up to 1,000 Hertz, and do those tasks well. But....

The large heat-dissipating transistors of the LDOs are large and with large junction areas and with large capacitances from input (unregulated voltage, or raw input) to output (which we expect to be well regulated at low frequencies, and which we forlornly and fruitlessly hope to magically become clean at all frequencies).

The large input-output capacitances of the large on-chip power devices provide a very-low-impedance for the ripple and the ringing that appears on output of a Switching Regulator.

Consider the ringing at 100MHz. With an assumed 100pF from unregulated raw input to the I-hope-this-is-clean output. What is the impedance of 100 pF at 100MHz?

1pf at 1Ghz is -j159 ohms.

100pF at 1Ghz is 1.59 ohms.

100pF at 100Mhz is 15.9 ohms

Thus your circuit using the LDO is like this:

schematic

simulate this circuit – Schematic created using CircuitLab

\$\endgroup\$
6
  • 1
    \$\begingroup\$ The switching frequencies I'm using are a little lower, about 500-600kHz. Also I'm using the TPS7A91 LDO regulator which claims to have a PSRR of 40dB at 1MHz. Should I still be concerned about ripple? To address the ringing I'm using ferrite beads on the power lines of sensitive components. Is that a reasonable solution to the ringing? \$\endgroup\$
    – MattHusz
    Dec 27, 2018 at 19:43
  • 1
    \$\begingroup\$ Reading that datasheet, the PSRR at 10MHz has just dropped to 15dB, down from 40dB at 1MHz. So you need to handle the 100 milliVolts of 100MHz ringing (5nH and 50pF of SwitchReg parasitic does produce 100MHz ringing). You can buy "X2Y" 4-terminal SMT caps with 0.5nanoHenry inductance. Visit their website. Consider using several PI filters (ones you construct on the PCB) between the LDO and the RF stuff that needs 0.1uvolt noise content (or whatever VDD trash budget you wish to use). At this point, design of the VDD filtering, and preserving the cleanliness, is a key design task. \$\endgroup\$ Dec 28, 2018 at 2:10
  • 1
    \$\begingroup\$ @ MattHusz What are your trash budgets in the VDD, at 0.8MHz and at 100MHz? \$\endgroup\$ Dec 28, 2018 at 2:15
  • 1
    \$\begingroup\$ still trying to get the answer for you, but this stuff is a bit new to me and I'm not quite sure. For instance, I have a 12-bit ADC (LTC2292) sampled at 40MHz and with a differential input of 1V (SNR of 71dB or higher). I think that would require the noise to be less than 0.3mV, but since that's 3 orders of magnitude higher than the 0.1uV you mentioned, I feel I might be missing something. \$\endgroup\$
    – MattHusz
    Dec 29, 2018 at 17:33
  • 1
    \$\begingroup\$ @ MattHusz Consider how a -140dBm noise floor may be needed. If you want -120dBm signal (approximately 0.6 microVolts PP RF) with +20dB SNR, then the trash entering --- thru an assumed 0dB PSRR for the RF_LNA/mixer/IFamp gain_chain --- must be at -140dBm which is about 0.06 microVolts PP (approx. 0.1uVPP) \$\endgroup\$ Dec 29, 2018 at 18:43

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.