I am designing a board with LM2596 voltage regulator (12V/5V 3A)

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I want to make heat-removing holes under the microcircuit. For this, I decided to use via holes. The board has two layers. The question is, is this the right solution? Or do they do the heat sink differently?

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    \$\begingroup\$ Unrelated to the heatsink question, but considering that this is a switching regulator I would consider redoing the layout with planes/polygons instead of traces (especially long thin traces). Look into reference designs and eval kits for examples. \$\endgroup\$ – Wesley Lee Dec 29 '18 at 15:38
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    \$\begingroup\$ Typically, the entire underside of the board would be one large ground plane. If you then use a bunch of via's underneath the chip it would act as both heatsink and a beefy low inductance ground connection. I'd also move the flywheel diode as close as possible to the output pin of the chip, use wider traces (polygons), add ceramic capacitance to the output and and take the feedback from the output capacitor in stead of from the inductor (see figure 32 in datasheet). \$\endgroup\$ – Unimportant Dec 29 '18 at 15:40
  • \$\begingroup\$ Also what are your goals for Tj max, Pd max , thus Rca max then SMD vs THT and did you look at ON Semi & TI land patterns? Can you ensure solder fill to entire area ? no \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 29 '18 at 15:48
  • \$\begingroup\$ @Unimportant, As a scheme, I used recommendations from Texas Instruments. Unfortunately, there was no mention of the output ceramic capacitor on the 5V line. Can you tell me which face value to choose? ti.com/lit/ds/symlink/lm2596.pdf \$\endgroup\$ – Delta Dec 29 '18 at 16:04
  • \$\begingroup\$ @WesleyLee, I had doubts about the correct layout, now I'm starting to change it for sure. \$\endgroup\$ – Delta Dec 29 '18 at 16:07

Each empty via (not solder-filled), if depth/periphery ratio is one:one and thus we can model the metal inside the via as a square of copper (plated) of proportion 1:1, and the plated copper is 35 microns (1.4 mils), the standard thickness of foil that is 1 ounce/foot^2 weight, has a THERMAL RESISTANCE of 70 degree Centigrade per watt of heat flow. And you need to let that heat spread out, on the backside of the PCB, or be taken to metal frame or case or chassis.

You have 4*5 vias in parallel, or about 70/20 = 3.5 degree C per watt, BUT all those 20 vias are transferring heat into the SAME tiny region of the back layer of foil.

You need a way to remove the heat from the 20 vias, but you have no way to remove the heat.

If you do add lots of backside foil, each square of foil offers the previously-mentioned 70 degree Centigrade per watt of thermal resistance.

Like this


simulate this circuit – Schematic created using CircuitLab

The thermal resistance of that first 3*3 ring of squares, around the central heat source, the 8 total squares in that ring, produce 70degreeC/8 = 9 degree Centigrade per watt of heat flow.

Each larger ring of squares (each square being 3:1 larger) also adds 9 degree Centigrade per watt.


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