MOSFET goes into saturation mode much later

Question

I am using IRLML6346 NMOS in LTSpice. Its threshold voltage is Vt = 0.95V. I plotted the graph of Vds(voltage between drain and source) vs Ids(Current from drain to source) for different values of Vgs(Voltage between gate and source)

I have written the gate voltage Vgs on the right below each plot and the approximate Vds value after which the NMOS goes into saturation mode.

For Vgs = 4.5, the saturation should start as soon as Vds >= Vgs - Vt. So it should go into saturation mode at 4.5 - 0.95 = 3.44. But in the plot, it goes into saturation at 5.4 volts. Similarly, for Vgs = 4, the saturation should start at 4 - 0.95 = 3.05, but it starts at Vds = 4V.

This same case happens for all the Vgs values. The saturation occurs much later. Why is this so?

This is the circuit I have made.

Why does the MOSFET does not go into saturation mode as soon as Vds >= Vgs - Vt?

Answer 1

You forgot about RdsOn * Ids.

Since Vds rises with Ids*RdsOn and Ids=Vds/RdsOn ,

I think linear Saturation is better defined as ;

\$V_{DS(sat)} >= V_{GS} - V_t + I_{DS}*R_{dsON}\$

You may sub RdsOn with another equation and reduce more.

Then $$I_{DS(sat)}<= k V_{DS}^2$$

REF