I am using IRLML6346 NMOS in LTSpice. Its threshold voltage is Vt = 0.95V. I plotted the graph of Vds(voltage between drain and source) vs Ids(Current from drain to source) for different values of Vgs(Voltage between gate and source)
For Vgs = 4.5, the saturation should start as soon as Vds >= Vgs - Vt. So it should go into saturation mode at 4.5 - 0.95 = 3.44. But in the plot, it goes into saturation at 5.4 volts. Similarly, for Vgs = 4, the saturation should start at 4 - 0.95 = 3.05, but it starts at Vds = 4V.
This same case happens for all the Vgs values. The saturation occurs much later. Why is this so?
This is the circuit I have made.
Why does the MOSFET does not go into saturation mode as soon as Vds >= Vgs - Vt?