I am using IRLML6346 NMOS in LTSpice. Its threshold voltage is Vt = 0.95V. I plotted the graph of Vds(voltage between drain and source) vs Ids(Current from drain to source) for different values of Vgs(Voltage between gate and source)

Plot of Ids vs Vds for different Vgs I have written the gate voltage Vgs on the right below each plot and the approximate Vds value after which the NMOS goes into saturation mode.

For Vgs = 4.5, the saturation should start as soon as Vds >= Vgs - Vt. So it should go into saturation mode at 4.5 - 0.95 = 3.44. But in the plot, it goes into saturation at 5.4 volts. Similarly, for Vgs = 4, the saturation should start at 4 - 0.95 = 3.05, but it starts at Vds = 4V.

This same case happens for all the Vgs values. The saturation occurs much later. Why is this so?

Mosfet Circuit it ltspice

This is the circuit I have made.

Why does the MOSFET does not go into saturation mode as soon as Vds >= Vgs - Vt?

  • \$\begingroup\$ Models in SPICE, in general, are not always the best representatives to the real world case, where even there tolerances and whatnot come into play. Still, they try to be as close as they can. Some succeed, some don't. Welcome to the "real world" of the simulators, and congratulations for taking the first step before using a model: verification. \$\endgroup\$ Commented Dec 30, 2018 at 8:33

1 Answer 1


You forgot about RdsOn * Ids.

Since Vds rises with Ids*RdsOn and Ids=Vds/RdsOn ,

I think linear Saturation is better defined as ;

\$V_{DS(sat)} >= V_{GS} - V_t + I_{DS}*R_{dsON}\$

You may sub RdsOn with another equation and reduce more.

Then $$I_{DS(sat)}<= k V_{DS}^2$$

enter image description here REF

  • \$\begingroup\$ I used this equation VDS(sat)>=VGS−Vt+IDS∗RdsON to find out RdsON at Vgs = 4.5 and Vt = 0.95(R comes out to be = 0.02196). I used this R value for other Vgs values and I got Vds for saturation very close to the simulation values. So this works. Thanks. But the MOSFET IRLML6346 NMOS model used has Ron 0.048 ohms in ltspice. Why is the calculated value different from the value I got. Any reason? Thank you. \$\endgroup\$
    – Keestu
    Commented Dec 30, 2018 at 7:18
  • \$\begingroup\$ Vt has a tolerance of 37.5% about 0.8V yet Ron is 46 mΩ typ and 63 mΩ max @ 4.5V, Id=3.4A for Vds*Id(Ron)=63mΩ*3.4A=214mV max rise so I'm not sure. Maybe worst case? Vt=1.1 \$\endgroup\$ Commented Dec 30, 2018 at 8:05

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