In Qsys, the address space is byte addressable. However, the datawidth of the master shall most likely be more than a byte. This could create a situation where sometimes a peripheral has wider data width than the master and at other times, a narrower data width than the master. I am sure that this complicates read and write accesses. e.g What if I want to read bytes in loop from a slave that has 16 bit data bus using a Nios that has a 32 bit data bus?
- Why doesn't Qsys use a fixed 32 or 64 bit data bus for all the components?
- How exactly does it get around the mismatch by inserting extra logic?