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I'm trying to get into IC layouts...

Why do I see some IC layouts with or without the body terminal on the transistors. Do MOSFet transistors need a body terminal in an integrated circuit? Or should I just ignore it, and just draw the source, gate, and drain (like most examples).

enter image description here enter image description here

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  • \$\begingroup\$ Please provide a link or other citation for the graphics you copied in your question. \$\endgroup\$ – Elliot Alderson Dec 30 '18 at 3:12
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I do not have enough reputation so I cannot ask this in the comment section. Do you have the technology documentation for the design you are working on? You should check it there regarding all the layout requirement you need to fulfill.

Now I try to answer. For standard CMOS process, you must have Body Bias. Body of PMOS (NMOS) should be connected to the highest (lowest) voltage available.

your first picture is just showing the cross section of the device. it is not complete and most of the time it is not, because the intention is just to show the cross sectional view of the device. It does not define the process. Again, to be sure, you should read the documentation of the technology you are using.

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  • \$\begingroup\$ Just to be complete, it is not required that the bodies be connected to the highest/lowest voltages in the circuit, as long as the body-to-source junctions are not forward biased. Varying the body voltage is one way of dynamically tweaking the threshold voltage. \$\endgroup\$ – Elliot Alderson Dec 30 '18 at 3:32
  • \$\begingroup\$ "Varying the body voltage is one way of dynamically tweaking the threshold voltage" ok, I did not know it before. I did not know whether this Vth tuning is available in standard CMOS. But now I remember I came across this Vth tuning when I was reading about FDSOI. \$\endgroup\$ – Codelearner777 Dec 30 '18 at 3:39
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The transistors you show need a body connection for proper operation. The body connection may be shared by many transistors and is not always shown explicitly on simple drawings.

For example, it is possible to use a conductive die attach so that the body of all NMOS transistors (the p substrate) is electrically connected to a metal pad in the bottom of the package cavity. A bond wire down to the metal pad provides a connection from a package pin to the body of all NMOS transistors, and this package pin would usually be grounded.

The situation is a little more complex for the PMOS transistors that are created in the n wells. There may be many separate n wells. Each n well might contain one or many PMOS transistors. Each n well must have its own n+ diffusion that is (usually) connected directly to the highest voltage in the circuit. Some processes will specify the maximum distance from a PMOS source/drain to the n well (body) connection.

In cases where you are worried about latchup you should provide low-resistance connections to the transistor bodies. For I/O pins it's not unusual to have a ring of n+ around the edge of the n well, for example.

Silicon-On-Insulator (SOI) transistor have much different characteristics and requirements for body connections.

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