I'm studying the following circuit enter image description here

The image is explicit but as you can see the input measured in the upper terminal is a square wave with \$E_c\$ and \$-E_c\$ as levels.

Now I also had no trouble understanding that if \$R_B \leq \beta R_C\$ when the square wave is in the positive half-cycle we have saturation and when it is on the negative half-cycle we have cutoff situation.

Now in saturation we will (because the junction voltages are zero) an output voltage of zero. That is correct with the figure. However when we are in cutoff, applying KVL to the output mesh leads us to


because currents can be neglected. That however is not concordant with the figure which shows $$U_{CE}=E_c$$ Why is that? What am I missing?

  • \$\begingroup\$ If the BJT is off, then there is no current in \$R_\text{C}\$ and therefore no voltage drop across it. So the collector will be the same as the applied voltage, \$+E_\text{C}\$. \$\endgroup\$ – jonk Dec 30 '18 at 7:43
  • \$\begingroup\$ That doesn't make sense :/ UCE will be equal to -EC because that is the input voltage with the transistor is cutoff \$\endgroup\$ – Granger Obliviate Dec 30 '18 at 14:48
  • \$\begingroup\$ I guess I don't understand what's preventing you from understanding things here. I'm also not sure if you feel you do understand it with the answer already given, or not. Do you need to see a different approach added to see if it catches you right? \$\endgroup\$ – jonk Dec 30 '18 at 19:43
  • \$\begingroup\$ Do you realize that your previous remark contradicts what's written bellow? My question was very simple, I just wanted someone to confirm me that the image is wrong because when we have an input of -EC we should have an output that is the same, instead of +EC. I already simulated the circuit in LTSpice and got this confirmed, so it's all good now, thank you. \$\endgroup\$ – Granger Obliviate Dec 30 '18 at 20:07
  • \$\begingroup\$ What I wrote is correct. But I'm glad to hear you feel you have what you need. Saves me time. Thanks. \$\endgroup\$ – jonk Dec 30 '18 at 20:14

I don't think the input is a square wave that has a negative half cycle. I think the dotted line between \$E_C\$ and \$-E_C\$ indicates a positive threshold voltage, and if the input falls below that threshold then the output will go high because the base current is too low to keep the transistor in saturation. There is no way that \$V_{CE}\$ can be positive, as indicated, if the only circuit supply voltage is negative.

Since this looks like homework I'll leave you to do the analysis.

It's not a very good schematic, in my opinion. Let's hope your textbook provides a good narrative to go along with it.

  • \$\begingroup\$ Hi! The input wave is correct (it is said explicitly in the book). Actually that I said above is confirmed in the book so like you said I find impossible that VCE is positive when we have -EC. The textbook is confusing. There was other circuit where this analysis is made that made total sense for me (a circuit with two voltage sources) but this one doesn't make sense \$\endgroup\$ – Granger Obliviate Dec 30 '18 at 14:43
  • \$\begingroup\$ what do you think? \$\endgroup\$ – Granger Obliviate Dec 30 '18 at 16:55
  • \$\begingroup\$ I think you should talk to the instructor about it. \$\endgroup\$ – Elliot Alderson Dec 30 '18 at 17:09

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.