I inherited a design that uses the following circuit to generate a 40MHz square wave clock signal:

enter image description here

KT2520K is a TCXO that outputs a clipped sine wave and the inverter has a peak output voltage of 3.3V. Is there any benefit to the inverter feedback configuration used here? In other designs I've seen one large-valued resistor used and without the C16 capacitor. I'm considering simplifying the design to use a single 931k resistor in place of R3, R8 and C16. Are there any drawbacks to this?

  • \$\begingroup\$ It would help a lot if we knew what peak output voltage is needed. Is it 1.8V, 3.3V, or 5V? I mention that because most would use a NPN transistor rated for UHF to amplify, then use logic gates with Schmitt trigger inputs to get a clean square wave. The 74AC02 and 74AC14 can run as fast as 150 MHZ. \$\endgroup\$ – user105652 Dec 30 '18 at 23:13
  • \$\begingroup\$ @Sparky256, I've edited the post to reflect the 3.3V output needed. \$\endgroup\$ – MattHusz Dec 31 '18 at 1:59

Normally a high impedance feedback for U5 would be to bias the inverter input and as bias for a bare crystal connected across U5 pins 2 and 4. Bare crystals run on microamps of current. Too much current can overheat the crystal causing much drift and a short life.

But what you have is a standalone TCXO with a buffered output. C13 is mandatory as the TCXO has a low operational voltage, not compatible with 3.3V or 5V logic. I have made logic inverters into amplifiers by using a buffered driver. To keep slew rates very fast I used a 33 ohm resistor at the input (it would be after C13), and a 3.3K resistor for feedback. I used a 74AC04 inverter but any very fast logic inverter will work.

My frequency counter worked up to 120 MHZ with a 100 mV sine wave signal. Since you have a strong 1 volt drive signal you could try the same. Now you have just the 2 resistors and C13. 3.3K is a much lower impedance less sensitive to noise and actually would not work without a strong drive signal.

The TCXO sees the 3.3K as its main load and the series 33 ohm resistor prevents the TCXO from 'seeing' the gate capacitance of U5, which prevents any tendency to have waveform overshoot or ringing. The 33 ohm combined with the 3.3K gives you a 1% 'dead zone' or about 33 mV where you have hysteresis, so noise less than 33 mV is ignored. You cannot increase the 33 ohm series resistor by much at all as it creates an RC filter based on the inverters input capacitance.

Ultimately the feedback resistor needs only to be of a high enough value so the TCXO input drives the inverter input both above and below its threshold voltage. With no input signal you want the DC value of U5 pin 2 to be no more than 1/2 Vcc, or about 1.65 volts. It is possible that due to its CMOS inputs a high value of feedback resistor was needed so pin was less than 1.0 V with no input signal. 3.3K may have to be as high as 33K or 330K. The lowest value that allows the circuit to always work is the one to use.

NOTE: Resistors do have a parasitic capacitance that is an issue above 50MHZ. If you need to split the value of the feedback resistor in half and insert C16 there. A large value of C16 helps to stabilise the DC part of the feedback loop, but it must have a very low ESR.

  • \$\begingroup\$ Is there some slew rate benefit to a larger feedback resistance? When I simulate this in spice it seems to have that effect. If that's true, does it make sense to increase the feedback resistance up to the point where the thermal noise voltage from the feedback resistance is still sufficiently less than the hysteresis? \$\endgroup\$ – MattHusz Dec 31 '18 at 17:24
  • \$\begingroup\$ I would agree with that, if you can measure such parameters. \$\endgroup\$ – user105652 Dec 31 '18 at 19:54
  • \$\begingroup\$ Would a bypass capacitor such as C16 help filter some of the Johnson noise? \$\endgroup\$ – MattHusz Jan 2 '19 at 16:51
  • \$\begingroup\$ Added NOTE section about C16. \$\endgroup\$ – user105652 Jan 2 '19 at 19:38

The action of that feedback is to apply the average value of U5's output onto its input. C13 then impresses the AC portion of U4's output onto U5's input.

So there's no AC feedback at all, implying no AC degeneration (or opportunity for oscillation, since that's a buffered inverter with presumably unpredictable, if not downright nasty, characteristics when you try to use it as an amplifier).

I would review the circuit to make sure that U4 has a high enough level output to reliably drive U5. I would not attempt to wrap a buffered inverter like that with an analog feedback loop -- I would expect that Bad Things would happen if I did.


Should you need low jitter (low phasenoise), then high value resistors may be a problem.

Also, the GROUNDs need to closely placed, with ground currents from other sources excluded.

Beware the power-supply rejection of a logic gate is very poor. Perhaps use a pre-amplifier (a miniCircuits?), to produce very high output slew-rate into the rail-rail logic gate.

If you have 1GHz bandwidth, and 10Kohm Rnoise in the first "amplifier" that touches the sin from the oscillator, you will have 12nanoVoltrms/rtHz, scaled by sqrt(1e+9) = 12e-9 * 3.1e+4 = 36e-5 = 360uVrms broadband random noise.

If the signal (the 40MHz), is 1vpeak * sin(40Mhz), the derivative is 1v * omega, or 1v * 40e+6 * 6.28, or the dV/dT is about 250 million volts per second.

Using the

OhmsLaw for jitter:

Tj = Vnoise/SlewRate

the best you can hope for is

360uV/250 million volts/second

or approximately 1 picosecond total integrated jitter.

Have you an error budget for this?


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