0
\$\begingroup\$

I'm taking apart a Pogoplug_V4_A1_V3.1, and I noticed this trace in a corner of a board, connected to the Marvell 88F6192 processor:

image of large part of board

closeup of pins

The trace itself is approx. 0.2Ω, and the resistor is approx. 0Ω. They are connected to pin 158 & 155, aka M_STARTBURST and M_STARTBURST_IN. According to the documentation:

Start Burst

88F619x indication of starting a burst read transaction. Asserted with the first M_CASn cycle of SDRAM access. NOTE: Must be routed on board to the SDRAM, and back to the 88F619x as M_STARTBURST_IN. For the recommended length calculation for this routing and termination requirements, see the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide.

This is interesting, because it's not connected to the SDRAM, it just goes in a big loop.

What is the purpose of this thing?

\$\endgroup\$
  • 3
    \$\begingroup\$ My guess would be that the total trace length is somehow matched to the traces going to/from the SDRAM, giving the processor the ability to measure the associated delay. \$\endgroup\$ – Dave Tweed Dec 31 '18 at 2:26
  • 1
    \$\begingroup\$ The xxx ps delay might also prevent a race condition for timing \$\endgroup\$ – Sunnyskyguy EE75 Dec 31 '18 at 2:33
  • 1
    \$\begingroup\$ Zig-zag patterns are a way of delaying data signals so they arrive at the same time. Clock and read/write strobes also use them as they need to arrive later than the data signals. As Dave Tweed mentioned in a comment there can be a isolated trace used as a flight-time reference. These chips measure time in nanoseconds or even picoseconds. \$\endgroup\$ – Sparky256 Dec 31 '18 at 3:59
4
\$\begingroup\$

The point is not to connect to the ram, but to provide a reference for the timing delay caused by the signal propagating to the ram. The thing probably drives startbust at the same time it dispatches the read burst command to the ram, but does not try to actually read until shortly after the startburst in pin becomes asserted.

It is a way to avoid having the configure the memory controller timings for each specific board layout.

I kind of wish more high speed memory interfaces did this, it would cut out a lot of annoying faffing about.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.