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I asked to design a sequence detector to detect 0110 and when this sequence happend turn it's output to 1 for 2 clock cycles.

Here is what I designed: enter image description here enter image description here

But the problem is it turns the output to 1, one clock cycle late IE if it encountered 0110 it doesn't turn output to 1 but instead it turns output to 1 on next positive edge of clk as you can see in below timing diagram.

I tried so much to solve it but I can't :( Can someone help me please

enter image description here

Edit: I have to add I know the problem is: y2 D flip flop is synchronised with Q1 D flip flop but what to do instead?

Edit 2:

New state diagram

enter image description here

Edit 3:

New state diagram

enter image description here

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  • \$\begingroup\$ Its also worth mentioning that you can use multiplexers to build FSMs too (in fact, this is the most common way). This is done by using the output bits from the flipflops as the address bits for the MUX, thus you can design most FSMs relatively easily using the transition table, without the need to solve Karnaugh maps. decoding Mealey and Moore outputs is then a fairly mundane task you are probably familiar with already :) \$\endgroup\$
    – Thefoilist
    Dec 31, 2018 at 15:59
  • \$\begingroup\$ yea I saw some texts which noted if you use one-hot encoding or etc. for the current-states part, may it makes your circuit more simple. you mean by using MUX then we don't need to check them? \$\endgroup\$
    – Me.
    Dec 31, 2018 at 18:32

1 Answer 1

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You need to come up with a state diagram (your very first step) that actually does what you want, before going through all of the detailed logic design.

With a Moore-type machine (outputs associated with states), it requires 5 states to recognize the sequence and then output a "1". Then, you need to replicate 2 of the states in order to output a "1" for a second clock while continuing to search for another copy of the pattern. Therefore, a total of 7 states is required.

I hope this is enough of a hint to get you on the right track.


Just for completeness, following your third edit, here is my version of the state diagram:

enter image description here

I find it helpful to label each state with what part of the sequence has been recognized so far. Some notes:

  • S0 represents finding 3 or more ones in a row. Since the pattern we're looking for starts with a zero, this also becomes our "start" state.

  • S1 represents finding any number of zeros, the last one of which could be the first bit of our pattern.

  • S4 represents finding the full pattern. The last bit is zero, which could also be the first bit of another pattern. Therefore, if the next bit is also zero, we go to state S1a, which is equivalent to S1, but with an output of "1". Similarly, if the next bit is "1", we've got the first two bits of a new pattern, so we go to S2a.

  • The transitions out of S1a are the same as those from S1, and the transitions from S2a are the same as those for S2.

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  • \$\begingroup\$ I didn't see any question like this before in our sourcebook, can you please give an example. oh and isn't there a way to store output in a shift register like what I did? \$\endgroup\$
    – Me.
    Dec 31, 2018 at 13:57
  • \$\begingroup\$ can you please check the new state diagram to see if is correct right now? if yes why not simply add one more state instead of two states? \$\endgroup\$
    – Me.
    Dec 31, 2018 at 14:18
  • \$\begingroup\$ You need two extra states because once you get to state S4 after recognizing the full sequence, you need to output a "1" on the next state after that regardless of whether the next input is "0" or "1". Your new diagram still does not do that -- if you get a "1" in state S4, you go to a state that outputs "0". \$\endgroup\$
    – Dave Tweed
    Dec 31, 2018 at 14:23
  • \$\begingroup\$ think got it, can you just see this too? thanks for your time \$\endgroup\$
    – Me.
    Dec 31, 2018 at 14:36
  • \$\begingroup\$ OK, your "Edit 3" version now looks like mine. You can proceed with the rest of the detailed design. \$\endgroup\$
    – Dave Tweed
    Dec 31, 2018 at 14:36

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