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I'm implementing a PID controller in software. Using P+D only doesn't bring me close enough to my set-point so I decided to also use an Integrator with Anti-Windup.

Question: In my Anti-Windup code - how do I decide on the upper and lower limits of the integrator ?

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    \$\begingroup\$ See Implementation integral windup in a digital proportional-integral controller. \$\endgroup\$
    – Transistor
    Dec 31, 2018 at 20:47
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    \$\begingroup\$ At a minimum, stop integrating when the output is saturated. Tim Wescott is a expert, maybe we'll see a definitive answer from him. \$\endgroup\$ Dec 31, 2018 at 22:29
  • \$\begingroup\$ An integrator can make it unstable unless you define the plant response that you are trying to compensate. Saturation reduces the gain to zero. \$\endgroup\$ Dec 31, 2018 at 22:54
  • \$\begingroup\$ Define your open loop function and test criteria for the design with any practical limits of any output. (-1 until you do this) \$\endgroup\$ Dec 31, 2018 at 23:03
  • \$\begingroup\$ What is the end purpose? An embedded PID inverted broom thesis? or?? \$\endgroup\$ Jan 1, 2019 at 16:21

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Question: In my Anti-Windup code - how do I decide on the upper and lower limits of the integrator ?

responses so far have been on how to implement anti-windup be it in comments or in responses. The question is actually HOW to decide on the values

Aspects of your system need to be understood and more specifically what the output is driving; is it another control loop or directly driving some actuator. You must have an idea.

Lets take a simple example

A velocity loop feeding a motor.

enter image description here

DEM is a voltage signal +-10V representing a velocity demand of +-100rpm (thus 1V = 10rpm)

FB is the feedback from some tacho such that 1V = 10rpm

Sig is the voltage that will be applied to the motor, equally of the same scaling of 1V = 10rpm.

The loops scalings are a design decision based upon feedback resolution and other implementation drivers.

Now I am showing anti-windup via the two sets of back-to-back zeners: One for the integrator and one for the final summation. Also shown is a reset for the integrator.

Now let's say I never want to command my motor to go > 80rpm, be it due to some safety concern or other considerations. I would need to limit the signals around the velocity PI controller to 80rpm => ~8V. In this case I would set the zeners to be 7v2. This way the integrator should not wind up to little over 7.8V (78rpm) and the final summation would equally be limited to 7.8V.

In this quick example I have set the domain scaling to be 10rpm per volt. In a digital controller you will also know the scaling of the variable's through the control loop ( 0.7A/lsb, 1rpm/lsb for instant) and equally you should know what you need to limit your control loops to (no more than 20Amps, no more than 50V).

Knowing the system constraints and knowing your implementation scalings, be it analogue or digital, is key in setting the appropriate gains as well as the appropriate limits

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  • \$\begingroup\$ This is just a PI controller with no D, yet I I a limit control with a switch dump in parallel controlled by? \$\endgroup\$ Jan 1, 2019 at 15:05
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    \$\begingroup\$ that is true there is no D term as this is just a discussion point. Adding in another OPAMP block doesn't change the fact a control loop needs to be understood and thus the physical quantity each loop is representing should be know. limiting is based upon what your maximum output demand is (be it 10,000rpm, 100A, 400V ...), the designer should know what the voltage/variable is referencing in the physical domain. This is why a simple PI is shown as a single loop driving a motor. This could easily be more elaborate but would obtrusify the importance of knowing what you are controlling. \$\endgroup\$
    – user16222
    Jan 1, 2019 at 16:19
  • \$\begingroup\$ Also your statement does not make any sense "yet I I a limit control with a switch dump in parallel controlled by?" What is "I I a limit". The switch is just there to be a bit more complete as all integration terms (hardware, software, digital) need to be resettable (powerup, inhibit etc) and thus providing some switch across the integrator C is needed, to be controlled via some higher logic/control. Again abstract to the main discussion of known what you are controlling and what different nodes represent: Vel -> Current (A/rpm) -> Voltage (V/A) \$\endgroup\$
    – user16222
    Jan 1, 2019 at 16:22
  • \$\begingroup\$ In reality there should be limits to outputs from each Kp, Ki, and Kd and initial conditions yes \$\endgroup\$ Jan 1, 2019 at 16:23
  • \$\begingroup\$ Ki is the most susceptible due to windup while Kp would exceed any inner demand with high gain and Kd with high error, these two can be catered for via the overall summation limit (always needed). \$\endgroup\$
    – user16222
    Jan 1, 2019 at 16:45
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Take a look at the following image ( figure 6.7 of https://www.cds.caltech.edu/~murray/courses/cds101/fa02/caltech/astrom-ch6.pdf)

This is how anti-windups are usually implemented. Basically, the output of your PID controller should already be properly scaled to your actuator (DAC, PWM, etc.) For example, if your actuator is a PWM with a limit between 0 and 100%, you should saturate the output (actuator model) so that it stays between 0 and 100%. If the output of PID is 110% for instance, the saturation block will clip it to 100%, yielding a 10% error that will be fed back to prevent the integrator wind-up.

Anti-windup example

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