I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level netlist, or is there a specific HLS synthesis tool? and how efficient is ASIC flow for HLS compared to RTL in terms of clock freq., area, and power? Does HLS C/C++ development really save the design time compared to RTL ?



bumped to the homepage by Community 2 days ago

This question has answers that may be good or bad; the system has marked it active so that they can be reviewed.

  • \$\begingroup\$ We used only RTL level at Intel when I was working as a team member on the P II and BX chipset. But that's two decades ago and we also had to use different synthesis tools, depending. I'm not up on current synthesis capabilities nor how powerful current tools are in targeting various and different ASIC FABs. I'd guess that there still isn't "one bright answer to all problems," though. So I will be wanting to see what kind of good answers you get here. \$\endgroup\$ – jonk Dec 31 '18 at 22:05
  • 3
    \$\begingroup\$ @jonk my experience is that HLS is really terrible. It’s okay, I guess, if you are not familiar with HDL and want something quickly for an FPGA. I wrote a few tests a few years ago and the HLS was at least an order of magnitude worse in performance with a couple of orders of magnitudes worse in area. \$\endgroup\$ – user110971 Dec 31 '18 at 22:20
  • \$\begingroup\$ I have been out of the industry for five years and I am also eager for an up-to-date answer. But seeing as the costs involved in ASIC design and the speed demands, I would think that HSL is not there for a long time. \$\endgroup\$ – Oldfart Dec 31 '18 at 22:21
  • \$\begingroup\$ @user110971 Thanks for the note. Quick question. How's the automated floorplanning these days? (It was worse than worthless two decades ago. I floorplanned almost everything by hand.) \$\endgroup\$ – jonk Dec 31 '18 at 23:22
  • \$\begingroup\$ @jonk What I have seen from the layout team: The major block areas and memories are placed by hand. (Blocks like: Processor, Video unit, Peripherals etc.) Also all analogue blocks are manually placed. But the placement and routing inside a block area is done automatically. \$\endgroup\$ – Oldfart Jan 1 at 0:02

Most toolchain manufacturers offer some form or other for HLS synthesis. But how good that is will depend highly on how much you pay. The cheap ones will, well, be cheap. And non-cheap means you pay a substantial amount of money every year for the tool. For most companies, it is thus more cost efficient to use people for HLS synthesis than paying for some tool.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.