53
\$\begingroup\$

I'm designing a 4 layer PCB and I know that the standard stack-up is

  1. Signals
  2. GND
  3. VCC
  4. Signals

(GND and VCC can be switched depending on the layer with more signals)

The problem is, I don't really want to connect all ground pins through vias, there are just too many of them. Maybe because I'm not used to 4 layer PCBs, anyway, I've read a tip by Henry W. Ott about a different stack-up

  1. GND
  2. Signals
  3. Signals
  4. GND

(Where the power is being routed with wide traces on the signal planes.)

According to him, this is the best stack-up possible with a four-layer PCB, for the following reasons:

  1. Signal layers are adjacent to ground planes.
  2. Signal layers are tightly coupled (close) to their adjacent planes.
  3. The ground planes can act as shields for the inner signal layers. (I think this requires stitching.)
  4. Multiple ground planes lower the ground (reference plane) impedance of the board and reduce the common-mode radiation. (I don't really understand this one.)

One problem is cross-talk, but I really don't have any signals in the third layer, so I don't think that cross-talk will be an issue with this stack-up. Am I correct in my assumption?

Note: The highest frequency is 48MHz and there's a WiFi module on the board, too.

\$\endgroup\$
1
  • 2
    \$\begingroup\$ Stackup discussions are useless, if you don't specify which planes are tightly spaced. \$\endgroup\$
    – tobalt
    Commented Jan 12, 2022 at 12:31

7 Answers 7

66
\$\begingroup\$

You will hate yourself if you do stack up number two ;) Maybe that's harsh but it's a going to be a PITA reworking a board with all internal signals. Don't be afraid of vias either.

Let's address some of your questions:

1.Signal layers are adjacent to ground planes.

Stop thinking about ground planes, and think more about reference planes. A signal running over a reference plane, whose voltage happens to be at VCC will still return over that reference plane. So the argument that somehow having your signal run over GND and not VCC is better is basically invalid.

2.Signal layers are tightly coupled (close) to their adjacent planes.

See number one I think the misunderstanding about only GND planes offering a return path leads to this misconception. What you want to do is keep your signals close to their reference planes, and at a constant correct impedance.

3.The ground planes can act as shields for the inner signal layers. (I think this requires stitching ??)

Yeah you could try to make a cage like this I guess, for your board you'll get better results keeping your trace to plane height as low as possible.

4.Multiple ground planes lower the ground (reference plane) impedance of the board and reduce the common-mode radiation. (don't really understand this one)

I think you've taken this to mean the more gnd planes I have the better, which is not really the case. This sounds like a broken rule of thumb to me.

My recommendation for your board based only on what you've told me is to do the following:

Signal Layer
(thin maybe 4-5mil FR4)
GND
(main FR-4 thickness, maybe 52 mil more or less depending on your final thickness)
VCC
(thin maybe 4-5mil FR4)
Signal Layer

Make sure you decouple properly.

Then if you really want to get into this go to amazon and buy either Dr. Johnson's High Speed Digital Design: A Handbook of Black Magic, or maybe Eric Bogatin's Signal and Power Integrity - Simplified. Read it love, live it :) Their websites have great information as well.

Good luck!

\$\endgroup\$
13
  • 1
    \$\begingroup\$ Great analysis! this is exactly what I was looking for, to understand why, I won't be using that stack-up now that I've seen the light :), thank you very much for the information, and the books too. \$\endgroup\$
    – mux
    Commented Sep 16, 2012 at 18:10
  • 2
    \$\begingroup\$ Could anyone explain the first point? What does it mean by saying signals running through a reference plane? As far as I know, signal runs from A to B and then from B to A through ground. \$\endgroup\$ Commented May 25, 2014 at 13:27
  • 2
    \$\begingroup\$ N.B. The free "Opamps for Everyone" chapter 17 gives pretty much the same advice as you did, which I've excerpted here before finding this question. \$\endgroup\$ Commented Oct 31, 2015 at 15:32
  • 2
    \$\begingroup\$ This answer was almost perfect until I got to your suggested stackup. That stackup will work perfectly well if all signals never leave their layers. However, a signal running on layer 1 will have its return current on GND. Add a via and move said signal to layer 4 and suddenly the return current has nowhere to go. A seperate return current PWR will develop, but for the return currents on layers 2 and 3 to meet, currents will go haywire all over the plane unless layers 2 and 3 are very close and practically one big capacitor which defeats the purpose of coupling layers 1 and 2, and 3 and 4. \$\endgroup\$
    – Anas Malas
    Commented Sep 28, 2022 at 12:17
  • 1
    \$\begingroup\$ @SomeHardwareGuy they serve to shunt frequencies below their resonance, which is typically 1-10 MHz depending on multiple factors :) \$\endgroup\$
    – Anas Malas
    Commented Nov 5, 2022 at 9:28
21
\$\begingroup\$

There is no such thing as THE best layer stackup. If you read carefully, the stackup with grounds on outer layers is said to be best from EMC perspective.

I don't like that configuration, though. Firstly, if your board uses SMT components, you'll have a lot more breaks in your planes. Secondly, any debugging or rework will be virtually impossible.

If you need to use such a configuration, you're doing something horribly wrong.

Also, there is nothing wrong with using vias for grounding. If you need to lower the inductance, just place more vias.

\$\endgroup\$
1
  • \$\begingroup\$ yes, there's no absolute best way of doing anything, I was asking with respect to my specific application, I don't have to use that configuration and I won't after reading the answers, thanks :) \$\endgroup\$
    – mux
    Commented Sep 16, 2012 at 17:59
14
\$\begingroup\$

"best" depends on the application. Theres really two questions to address in your post

  1. "Conventional" (signals on outer layers, planes on inner layers) VS "inside-out" (signals on inner layers, planes on outer layers).
    An inside-out board will have better EMC performance but it will be much harder to modify when you realise you screwed up the design, will need more vias which is not great from a density or signal integrity point of view and if you are using IC packages whose pin pitch is too small to put ground between the pads then you end up with big holes in your planes which is also not great from a signal itegrity perspective.

  2. two ground planes VS one ground plane and one power plane.
    In both cases when a high speed signal changes reference plane there needs to be a nearby path for it's return current to move between the two reference planes. With two ground planes you can do that with a single via connecting the two planes directly. With ground and power planes the connection has to go via a capacitor which typically (assuming a "conventional" stackup) requires two vias and a capacitor. That means worse signal integrity and more board area taken up. On the other hand having a power plane reduces volt drop on your power rail and frees up space on your signal layers.

\$\endgroup\$
11
\$\begingroup\$

As the others said, it depends on your application. Another stackup I've found useful is

  1. Signals (low speed)
  2. Power
  3. Signals (impedance controlled)
  4. GND

This keeps the two signal groups well isolated from each other, gives excellent impedance matching and allows me to dump heat into the ground plane.

\$\endgroup\$
3
  • 3
    \$\begingroup\$ Why was this answer downvoted? The only reason I can think of is that the impedance controlled traces being on a inner layer means that they'll always need vias from the SMD pads to said layer which might not be "ideal", but other than that it seems like a perfectly valid answer, particularly since the vias might not even be a problem. \$\endgroup\$
    – Chi
    Commented Aug 1, 2019 at 0:37
  • 1
    \$\begingroup\$ some people a religous when it comes to stackups and routing, every answer is going to offend someone. \$\endgroup\$ Commented Nov 28, 2022 at 22:50
  • 1
    \$\begingroup\$ This stack-up might work in many applications, so don't take this comment too seriously. But it will have a tendency for asymmetric vertical copper distribution, the impedance controlled signals have their fields in the space where the power comes from (crosstalk) and a dedicated power plane is often not necessary in a 4 layer design. Overall I don't think it's a good stack-up to default to, although it will work just fine or may even be the optimal trade-off depending on the application. \$\endgroup\$
    – feynman
    Commented Dec 23, 2022 at 15:21
11
\$\begingroup\$

Sig-GND-PWR-Sig will work just fine in many applications. However, I would not recommend it as a default choice.

What I personally use as default stack-up is this one:

  1. Sig + Routed and/or Poured Power
  2. GND
  3. GND
  4. Sig + Routed and/or Poured Power

I'm assuming a standard build-up with relatively thin prepregs under the outer layers and a relatively thick core between the inner layers (which would also be the preferred build-up for Sig-GND-PWR-Sig by the way).

Some aspects about this stack-up:

  • In many cases, circuits on a four-layer PCB will not have very demanding requirements for the power distribution network (PDN). So chances are you don't need a dedicated power plane.
  • Every single trace (Signal and Power) has a close-by reference plane, which reduces cross-talk and radiation (less spreading of fields).
  • Since both reference planes are on the same DC potential, you can place return vias next to signal vias providing a reasonably well defined return path even when changing layers (again, less field spreading).
  • Traces are accessible for debugging/rework.
  • It is missing the "Faraday cage" shielding feature of GND-Sig-Sig-GND. But traces over close-by reference planes are already very bad antennas. The additional shielding of GND-Sig-Sig-GND should be negligible in many applications.

Of course, GND-Sig-Sig-GND is still one of the better four-layer stack-ups.

Depending on the application, many stack-ups will work just fine. There simply isn't a "best" or "worst" stack-up. But there are certainly stack-ups that are "better" to default to. At the very least it doesn't hurt to be aware of the different up- and downsides of different configurations.

Regarding one of your questions:

Multiple ground planes lower the ground (reference plane) impedance of the board and reduce the common-mode radiation. (I don't really understand this one.)

I guess, this is about cable radiation. Multiple ground planes lower the impedance (inductance) and thus lower voltage noise on the planes. That voltage noise can couple onto cables that are attached to your board an cause common-mode currents on these cables. Common-mode currents on cables are a major source for radiated emission failures.

\$\endgroup\$
1
  • \$\begingroup\$ After many years of favourites that have come and go, this is probably now my go-to. In very exceptional cases, inside-out is useful. I used to favour a PWR plane, but the typical ~1mm gap means there's negligible distributed capacitance benefit, and signals switching from top to bottom will have to jump reference planes, and power is usually segmented enough that a single pour isn't super convenient anyway. So pour ground, route key signals, route power, route the rest, and then pour in the gaps. Designating a layer for horizontal/vertical traces can probably be by preference. \$\endgroup\$ Commented Apr 11, 2023 at 2:24
4
\$\begingroup\$

While this is an old question, I felt the need to answer as I think Some Hardware Guy's recommended stackup of [sig gnd pwr sig] is not ideal unless the entire PCB is 0.6mm or less thick, instead I will advocate for [sig+pwr gnd gnd sig+pwr] making sure that layers 1 and 2 are less than 0.25mm apart, same for layers 3 and 4. Also, I didnt feel it was clarified well enough that choosing a stackup refers to multiple things together:

  1. Layer count
  2. How each layer is used
  3. Layer to layer spacing

Background

Firstly, ask 10 experts what's best and youll get multiple correct answers that conflict, because "best" doesnt mean much. It can be best for ease of routing, best for PCB copper balancing, best for signal integrity, best for cost, best for crosstalk, etc. You probably mean best overall, but who's choosing what matters and what doesn’t?

Pedantry aside, let’s start with spacing.

Compared to layer pairs like [1 2 3 4], if layers are equidistant [1 2 3 4], you would need larger trace seperation to maintain signal integrity, and traces need to be much bigger to be the same impedance. This would be even worse if you choose the middle two layers to be planes and made them near each other [1 2 3 4]. If you make layers 1 and 2 a pair, then 3 and 4 a pair [1 2 3 4], you can have relatively small, close together traces with the same impedance and crosstalk. The only reason to have layers 2 and 3 close would be if you are forced to have a ground and power plane.

So, what should we use each layer for? We must remember two things: Each signal needs an unbroken return close to it throughout its entire path, and distance is king in this discussion. When a signal travels over a plane, a return current will form. This current will flow in such a way that more of it will go through the lowest impedance path. At DC, this current will look like a puddle as the lowest impedance path (here, purely resistive) is close in impedance to many paths along the plane, but when a high frequency signal is sent through the trace, the lowest impedance path for the return current is one with the highest capacitance and least inductance, which happens to be directly under the trace following its exact shape and is MUCH lower in impedance than any other copper, so even if a shorter path exists, the vast majority will travel in that one path. So even with a continious plane, at high frequency you might as well remove the plane and add a mirror return trace under the signal trace and there will be no difference, which I think highlights why an unbroken return path is necessary. You can read more about this here. Almost every single board made today contains high frequency, even if it is just an MCU with an integrated oscillator blinking an LED, the rise time of the LED line is extremely small, so high frequency content exists even in that example.

Sig/gnd/pwr/sig stackup has two problems: smallest of which is that by using this stackup, pwr's return path is very far away. Bigger than this is that a signal going from layer 1 to 4 will have a broken return path, this will lead to two return paths that follow the signals until the via, then go haywire across the board until a connection point is done, such as all nearby decoupling capacitors and other places where you really dont want it. That is unless you get layers 2 and 3 really close together to have enough interplane capacitance to pass this return current at high frequency, which would result in signals on layers 1 and 4 being large and seperated. This stackup with layer pairs being [1 2 3 4] is only ok if a signal never leaves on layer and goes to another, and if the signal passes over a reference plane (which would probably be gnd, and the same pwr that the signal comes from, for example a 0/5V signal can pass over 0V or 5V, but not -5V or 12V).

Conclusion

If you use two signal layers, you almost must use two of the same plane layers (both gnd, or both the same pwr which the entire circuit uses. This may be better if ground connections are relatively few to pwr ones). Whatever doesnt get its own plane has to share a layer, which is usually sig and pwr sharing the same layer, with routed or poured power. As distance is king, you cannot have only one ground plane with two signal layers as in [sig gnd sig pwr]. If two signal layers are used with two identical reference planes, each signal via must have a "stitching" via as close to it as possible, connecting both reference planes. As long as you follow these rules, you can have many choices. Even unusual options may be better for your specific project. As a starting point, I recommend the following stackup: [sig+pwr gnd gnd sig+pwr]. I usually leave layer 1 for routed power, and if layer 4 is sparse I do a copper pour for pwr (while keeping the pour away from signals not referenced to it, or having multiple pours for different areas requiring a different voltage).

Quick note

You can make good arguments for the use of either the suggested [gnd sig+pwr sig+pwr gnd] or [sig+pwr gnd gnd sig+pwr], each is better in different ways, but the former does not suffer from more crosstalk in any meaningful way, this is because one sig layer is much closer to gnd than the other sig+pwr layer, which is why it isnt meaningfully better than [gnd sig+pwr gnd sig+pwr] for a standard 1.6mm PCB where layer 1 is significantly closer to layer 2 than 3.

\$\endgroup\$
13
  • 1
    \$\begingroup\$ Counterpoint: signals go "across the board" regardless. Proof: a PCB is an EM structure, a network, made of finite size and resistivity; the attenuation between any two points is finite. Specifically for the between-planes mode (which is more specifically a 2D (plane) waveguide), vias couple into this mode. Transiently, a signal edge into a via, spreads out radially, so experiences an impedance Z(t) ~ μ_0 h/t, for plane spacing h. The same is true for a stitch via (for GND-GND) or bypass (for GND-PWR): an incident wave isn't terminated, but scattered. \$\endgroup\$ Commented Sep 28, 2022 at 15:13
  • 1
    \$\begingroup\$ Sorry, but you’ve hit me pet peeve here ”When a signal travels over a plane, a return current will form. It will take the lowest impedance path”. Signals do not take the path of least resistance, rather it will divide itself to minimize the total losses. Draw a schematic of a voltage with two paths to ground, one 1000 ohm and one other with 1001 ohm. Will all the current flow in the 1000 ohm path and nothing in the 1001 ohm dito? \$\endgroup\$
    – winny
    Commented Sep 28, 2022 at 15:18
  • 1
    \$\begingroup\$ We can say that a signal spreads out less [implied: for a given magnitude at a distance, or for an LF equivalent self-inductance] for closer planes, and so this might be valuable for higher frequency, lower impedance, or more compact designs. And we can design signal currents and plane impedance such that the remaining disturbance (supply ripple/noise) at any nearby node is acceptably low (for most digital, even some ~mV is low). The problem with the tradeoff is that it's not simply which EM structure is better: it's also what you're capable of. \$\endgroup\$ Commented Sep 28, 2022 at 15:18
  • 1
    \$\begingroup\$ For 99% of things (MCUs and other general digital stuff, analog not at low level or RF, etc.), sig/gnd/pwr/sig is the easiest for a beginner to lay out while having the best chance of success, and the fastest for a professional to lay out. Simply reducing the routing complexity by putting the two biggest nets onto "skyhooks" as it were, saves so much effort -- and almost completely removes concerns about local bypassing, which is much more critical when power is routed as just another signal. \$\endgroup\$ Commented Sep 28, 2022 at 15:20
  • 1
    \$\begingroup\$ (...Maybe I should just toss these comments into my own answer, but these notes aren't even a complete answer. Which... goes to show why engaging in EMC discussions on a non-discussion-forum...kind of stinks. Readers beware, I guess.) \$\endgroup\$ Commented Sep 28, 2022 at 15:22
1
\$\begingroup\$

I think the second one is better, because most stuff is ground referenced anyway (including power) so you can just route everywhere.

I usually use a variation of this, which has the two GND layers internal and uses the external layers for routing. That way I can avoid vias for a lot of stuff which can be directly connected on the external layers. I don't think that the GND planes being internal has much bad consequences on emissions. The tight coupling is the same and the component leads are outside anyway.

If I were in a situation which genuinely needs a lot of plane capacitance for power supply, I wouldn't use 4 layers but add a tightly coupled POW+GND plane pair to the stack. This only really matters for extremely fast chips that have stringent power supply impedance requirements at multi-GHz frequencies.

Having said that, most manufacturers' stack ups I know don't have the inner two planes tightly coupled in a 4 layer board by default. That means that POW+GND on those layers will be not so amazing as one could hope for. And for a low frequency design, the first stackup is a pure waste of board space due to that power plane.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.