I'm trying to understand how this circuit works on the input stage to the 4192A Impedance Analyzer.

4192A Impedance Analyzer Transimpedance Frontend

Apologies for the quality... this is the best scan I could find. The design is furnished with the following explanation:

In parallel with the basic feedback loop (R145) for the current to voltage function, the secondary loop, consisting of R132, C112, and the class C bias push-pull amplifier stage (Q30 and Q31) applies a non-linear feedback to suppress the output for excessive inputs. Normally, both Q30 and Q31 are off with no base bias. Over almost the entire voltage range of the amplifier output, the secondary feedback loop is open, so the I-V converter amplifier has a linear gain characteristic. When a transient unbalance input approaches the saturation level of the amplifier, Q30 and Q31 turn on in the peak region of the output before saturation occurs. As the secondary feedback loop decreases the gain of the I-V converter, further increase in the output voltage is suppressed. It moderates the saturation of the amplifier and, consequently, prevents a phase shift at the output (an effect of saturation). [From the 4192A service manual]

First of all, I want to ask if, after eliminating Q30 and Q31, there's a way to see how the described phase shift comes about near saturation. Is this a property of op-amps in general or just the way this amplifier is designed? This circuit is a kind of high gain amplifier with feedback and acts like an op-amp, right? Finally, I don't understand how adding Q30 and Q31 would cause the output to clip in a way that has less of a phase shift than driving the amplifier into saturation without Q30 and Q31 would. The only kind of phase shifting nonlinearity I understand is slew-induced distortion. Is that what they're referring to? I guess I can understand how using feedback to reduce the gain would reduce the slew rate, but the slewing is fastest near zero volts, which is where Q30 and Q31 are not reducing the gain. I had thought maybe the answer is in the time constant from R132 and C112, but this is only 316 ohms * 4.7 pF = 1.5 ns

Thanks in advance for having a look!

EDIT: Another thought. Could the phase shift be contributed by the amplifier's recovery time once driven into saturation? As in... if some of the BJTs are driven into saturation, I suppose you have to wait to remove the stored charge from the base before they come out of saturation and the amplifier responds. When the description says "saturation," do they perhaps not just mean "not railed," but also "no transistors are driven out of the active regime"


Until that topmost PNP turns on, nothing happens in the other 5 transistors, as far as I can tell from the schematic.

Its a hard-to-read drawing.

I've done similar circuits (high speed input clamps) on photodiode amplifiers for IRDA


simulate this circuit – Schematic created using CircuitLab


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